153 lines
4.7 KiB
C
153 lines
4.7 KiB
C
/*
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <asm/guest/vm.h>
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#include <errno.h>
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#include <vpci.h>
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#include <asm/guest/ept.h>
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#include <asm/mmu.h>
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#include <logmsg.h>
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#include "vpci_priv.h"
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/**
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* @brief Writing MSI-X Capability Structure
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*
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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*/
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bool write_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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static const uint8_t msix_ro_mask[12U] = {
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0xffU, 0xffU, 0xffU, 0x3fU, /* Only Function Mask and MSI-X Enable writable */
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0xffU, 0xffU, 0xffU, 0xffU,
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0xffU, 0xffU, 0xffU, 0xffU };
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bool is_written = false;
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uint32_t old, ro_mask = ~0U;
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(void)memcpy_s((void *)&ro_mask, bytes, (void *)&msix_ro_mask[offset - vdev->msix.capoff], bytes);
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if (ro_mask != ~0U) {
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old = pci_vdev_read_vcfg(vdev, offset, bytes);
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pci_vdev_write_vcfg(vdev, offset, bytes, (old & ro_mask) | (val & ~ro_mask));
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is_written = true;
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}
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return is_written;
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}
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/**
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* @pre vdev != NULL
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* @pre io_req != NULL
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* @pre mmio->address >= vdev->msix.mmio_gpa
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*/
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uint32_t rw_vmsix_table(struct pci_vdev *vdev, struct io_request *io_req)
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{
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struct acrn_mmio_request *mmio = &io_req->reqs.mmio_request;
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struct msix_table_entry *entry;
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uint32_t entry_offset, table_offset, index = CONFIG_MAX_MSIX_TABLE_NUM;
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uint64_t offset;
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/* Must be full DWORD or full QWORD aligned. */
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if ((mmio->size == 4U) || (mmio->size == 8U)) {
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offset = mmio->address - vdev->msix.mmio_gpa;
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if (msixtable_access(vdev, (uint32_t)offset)) {
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table_offset = (uint32_t)(offset - vdev->msix.table_offset);
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index = table_offset / MSIX_TABLE_ENTRY_SIZE;
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entry = &vdev->msix.table_entries[index];
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entry_offset = table_offset % MSIX_TABLE_ENTRY_SIZE;
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if (mmio->direction == ACRN_IOREQ_DIR_READ) {
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(void)memcpy_s(&mmio->value, (size_t)mmio->size,
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(void *)entry + entry_offset, (size_t)mmio->size);
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} else {
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(void)memcpy_s((void *)entry + entry_offset, (size_t)mmio->size,
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&mmio->value, (size_t)mmio->size);
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}
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} else if (mmio->direction == ACRN_IOREQ_DIR_READ) {
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mmio->value = 0UL;
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}
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} else {
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pr_err("%s, Only DWORD and QWORD are permitted", __func__);
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}
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return index;
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}
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/**
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* @pre io_req != NULL
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* @pre priv_data != NULL
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*/
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int32_t vmsix_handle_table_mmio_access(struct io_request *io_req, void *priv_data)
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{
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(void)rw_vmsix_table((struct pci_vdev *)priv_data, io_req);
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return 0;
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}
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/**
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* @pre vdev != NULL
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*/
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int32_t add_vmsix_capability(struct pci_vdev *vdev, uint32_t entry_num, uint8_t bar_num)
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{
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uint32_t table_size, i;
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struct msixcap msixcap;
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int32_t ret = -1;
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if ((bar_num < PCI_BAR_COUNT) &&
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(entry_num <= min(CONFIG_MAX_MSIX_TABLE_NUM, VMSIX_MAX_TABLE_ENTRY_NUM))) {
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table_size = VMSIX_MAX_ENTRY_TABLE_SIZE;
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vdev->msix.caplen = MSIX_CAPLEN;
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vdev->msix.table_bar = bar_num;
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vdev->msix.table_offset = 0U;
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vdev->msix.table_count = entry_num;
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/* set mask bit of vector control register */
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for (i = 0; i < entry_num; i++) {
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vdev->msix.table_entries[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
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}
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(void)memset(&msixcap, 0U, sizeof(struct msixcap));
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msixcap.capid = PCIY_MSIX;
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msixcap.msgctrl = (uint16_t)entry_num - 1U;
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/* - MSI-X table start at offset 0 */
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msixcap.table_info = bar_num;
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msixcap.pba_info = table_size | bar_num;
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vdev->msix.capoff = vpci_add_capability(vdev, (uint8_t *)(&msixcap), sizeof(struct msixcap));
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if (vdev->msix.capoff != 0U) {
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ret = 0;
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}
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}
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return ret;
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}
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