317 lines
13 KiB
Python
317 lines
13 KiB
Python
# Copyright (C) 2019 Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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import sys
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import enum
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import board_cfg_lib
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import common
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class RDT(enum.Enum):
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L2 = 0
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L3 = 1
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MBA = 2
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INCLUDE_HEADER = """
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#include <asm/board.h>
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#include <asm/vtd.h>
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#include <asm/msr.h>
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#include <pci.h>
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#include <misc_cfg.h>
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"""
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MSR_IA32_L2_MASK_BASE = 0x00000D10
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MSR_IA32_L2_MASK_END = 0x00000D4F
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MSR_IA32_L3_MASK_BASE = 0x00000C90
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MSR_IA32_L3_MASK_END = 0x00000D0F
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def gen_dmar_structure(config):
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"""Generate dmar structure information"""
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dmar_info_lines = board_cfg_lib.get_info(common.BOARD_INFO_FILE, "<DRHD_INFO>", "</DRHD_INFO>")
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drhd_cnt = 0
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drhd_dev_scope_cnt = []
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dev_scope_type = []
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if not dmar_info_lines:
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print("\n#ifndef CONFIG_ACPI_PARSE_ENABLED", file=config)
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print("#error \"DMAR info is not available, please set ACPI_PARSE_ENABLED to y. \\", file=config)
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print("\tOr use acrn-config tool to generate platform DMAR info.\"", file=config)
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print("#endif\n", file=config)
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print("struct dmar_info plat_dmar_info;\n", file=config)
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return
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# parse to get DRHD count and dev scope count
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for dmar_line in dmar_info_lines:
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if "DRHD_COUNT" in dmar_line and not drhd_cnt:
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drhd_cnt = int(dmar_line.split()[2].strip('U'))
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for i_cnt in range(drhd_cnt):
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for dmar_line in dmar_info_lines:
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dev_scope_cnt_str = "DRHD{}_DEV_CNT".format(i_cnt)
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if dev_scope_cnt_str in dmar_line:
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tmp_dev_scope_cnt = int(dmar_line.split()[2].strip('U'), 16)
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drhd_dev_scope_cnt.append(tmp_dev_scope_cnt)
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# gen dmar structure information
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for i_drhd_cnt in range(drhd_cnt):
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dev_cnt = drhd_dev_scope_cnt[i_drhd_cnt]
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print("static struct dmar_dev_scope drhd{}_dev_scope[DRHD{}_DEV_CNT] = {{".format(
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i_drhd_cnt, i_drhd_cnt), file=config)
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for i_dev_cnt in range(dev_cnt):
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print("\t{", file=config)
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print("\t\t.type = DRHD{}_DEVSCOPE{}_TYPE,".format(i_drhd_cnt, i_dev_cnt), file=config)
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print("\t\t.id = DRHD{}_DEVSCOPE{}_ID,".format(i_drhd_cnt, i_dev_cnt), file=config)
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print("\t\t.bus = DRHD{}_DEVSCOPE{}_BUS,".format(i_drhd_cnt, i_dev_cnt), file=config)
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print("\t\t.devfun = DRHD{}_DEVSCOPE{}_PATH,".format(i_drhd_cnt, i_dev_cnt), file=config)
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print("\t},", file=config)
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print("};", file=config)
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print("", file=config)
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print("static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {", file=config)
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for i_drhd_cnt in range(drhd_cnt):
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print("\t{", file=config)
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print("\t\t.dev_cnt = DRHD{}_DEV_CNT,".format(i_drhd_cnt), file=config)
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print("\t\t.segment = DRHD{}_SEGMENT,".format(i_drhd_cnt), file=config)
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print("\t\t.flags = DRHD{}_FLAGS,".format(i_drhd_cnt), file=config)
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print("\t\t.reg_base_addr = DRHD{}_REG_BASE,".format(i_drhd_cnt), file=config)
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print("\t\t.ignore = DRHD{}_IGNORE,".format(i_drhd_cnt), file=config)
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print("\t\t.devices = drhd{}_dev_scope".format(i_drhd_cnt), file=config)
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print("\t},", file=config)
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print("};", file=config)
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print("", file=config)
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print("struct dmar_info plat_dmar_info = {", file=config)
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print("\t.drhd_count = DRHD_COUNT,", file=config)
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print("\t.drhd_units = drhd_info_array,", file=config)
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print("};", file=config)
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def populate_clos_mask_msr(rdt_res, cat_mask_list, config):
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"""
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Populate the clos bitmask and msr index for a given RDT resource
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:param rdt_res: it is a string representing the RDT resource
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:param cat_mask_list: cache mask list corresponding to each CLOS
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:param config: it is a file pointer of board information for writing to
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"""
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idx = 0
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for cat_mask in cat_mask_list:
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print("\t{", file=config)
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print("\t\t.value.clos_mask = CLOS_MASK_{},".format(idx), file=config)
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print("\t\t.msr_index = MSR_IA32_{0}_MASK_BASE + {1},".format(
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rdt_res, idx), file=config)
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print("\t},", file=config)
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idx += 1
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def populate_mba_delay_mask(rdt_res, mba_delay_list, config):
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"""
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Populate the mba delay mask and msr index for memory resource
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:param rdt_res: it is a string representing the RDT resource
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:param mba_delay_list: mba delay value list corresponding to each CLOS
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:param config: it is a file pointer of board information for writing to
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"""
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idx = 0
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for mba_delay_mask in mba_delay_list:
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print("\t{", file=config)
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print("\t\t.value.mba_delay = MBA_MASK_{},".format(idx), file=config)
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print("\t\t.msr_index = MSR_IA32_{0}_MASK_BASE + {1},".format(
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rdt_res, idx), file=config)
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print("\t},", file=config)
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idx += 1
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def gen_rdt_res(config):
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"""
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Get RDT resource (L2, L3, MBA) information
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:param config: it is a file pointer of board information for writing to
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"""
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err_dic = {}
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rdt_res_str =""
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res_present = [0, 0, 0]
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(rdt_resources, rdt_res_clos_max, _) = board_cfg_lib.clos_info_parser(common.BOARD_INFO_FILE)
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common_clos_max = board_cfg_lib.get_common_clos_max()
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cat_mask_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "CLOS_MASK")
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mba_delay_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "MBA_DELAY")
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if common_clos_max > MSR_IA32_L2_MASK_END - MSR_IA32_L2_MASK_BASE or\
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common_clos_max > MSR_IA32_L3_MASK_END - MSR_IA32_L3_MASK_BASE:
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err_dic["board config: generate board.c failed"] = "CLOS MAX should be less than reserved adress region length of L2/L3 cache"
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return err_dic
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print("\n#ifdef CONFIG_RDT_ENABLED", file=config)
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if len(rdt_resources) == 0 or common_clos_max == 0:
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print("struct platform_clos_info platform_{0}_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];".format("l2"), file=config)
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print("struct platform_clos_info platform_{0}_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];".format("l3"), file=config)
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print("struct platform_clos_info platform_{0}_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];".format("mba"), file=config)
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else:
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for idx, rdt_res in enumerate(rdt_resources):
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if rdt_res == "L2":
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rdt_res_str = "l2"
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print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str,
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"MAX_CACHE_CLOS_NUM_ENTRIES"), file=config)
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populate_clos_mask_msr(rdt_res, cat_mask_list, config)
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print("};\n", file=config)
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res_present[RDT.L2.value] = 1
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elif rdt_res == "L3":
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rdt_res_str = "l3"
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print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str,
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"MAX_CACHE_CLOS_NUM_ENTRIES"), file=config)
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populate_clos_mask_msr(rdt_res, cat_mask_list, config)
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print("};\n", file=config)
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res_present[RDT.L3.value] = 1
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elif rdt_res == "MBA":
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rdt_res_str = "mba"
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print("struct platform_clos_info platform_{0}_clos_array[{1}] = {{".format(rdt_res_str,
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"MAX_MBA_CLOS_NUM_ENTRIES"), file=config)
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err_dic = populate_mba_delay_mask(rdt_res, mba_delay_list, config)
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print("};\n", file=config)
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res_present[RDT.MBA.value] = 1
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else:
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err_dic['board config: generate board.c failed'] = "The input of {} was corrupted!".format(common.BOARD_INFO_FILE)
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return err_dic
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if res_present[RDT.L2.value] == 0:
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print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("l2", "MAX_CACHE_CLOS_NUM_ENTRIES"), file=config)
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if res_present[RDT.L3.value] == 0:
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print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("l3", "MAX_CACHE_CLOS_NUM_ENTRIES"), file=config)
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if res_present[RDT.MBA.value] == 0:
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print("struct platform_clos_info platform_{0}_clos_array[{1}];".format("mba", "MAX_MBA_CLOS_NUM_ENTRIES"), file=config)
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print("#endif", file=config)
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print("", file=config)
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return err_dic
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def gen_single_data(data_lines, domain_str, config):
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line_i = 0
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data_statues = True
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data_len = len(data_lines)
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if data_len == 0:
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return
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for data_l in data_lines:
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if line_i == 0:
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if "not available" in data_l:
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print(data_l.strip(), file=config)
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print("static const struct acrn_{}state_data board_cpu_{}x[0];".format(domain_str, domain_str), file=config)
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print("", file=config)
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data_statues = False
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break
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else:
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print("static const struct acrn_{}state_data board_cpu_{}x[{}] = {{".format(domain_str, domain_str, data_len), file=config)
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print("\t{0}".format(data_l.strip()), file=config)
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line_i += 1
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if data_statues:
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print("};\n", file=config)
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def gen_px_cx(config):
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"""
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Get Px/Cx and store them to board.c
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:param config: it is a file pointer of board information for writing to
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"""
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cpu_brand_lines = board_cfg_lib.get_info(
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common.BOARD_INFO_FILE, "<CPU_BRAND>", "</CPU_BRAND>")
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cx_lines = board_cfg_lib.get_info(common.BOARD_INFO_FILE, "<CX_INFO>", "</CX_INFO>")
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px_lines = board_cfg_lib.get_info(common.BOARD_INFO_FILE, "<PX_INFO>", "</PX_INFO>")
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gen_single_data(cx_lines, 'c', config)
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gen_single_data(px_lines, 'p', config)
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if not cpu_brand_lines:
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print("\nconst struct cpu_state_table board_cpu_state_tbl;\n", file=config)
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return
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for brand_line in cpu_brand_lines:
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cpu_brand = brand_line
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print("const struct cpu_state_table board_cpu_state_tbl = {", file=config)
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print("\t{0},".format(cpu_brand.strip()), file=config)
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print("\t{(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px,", file=config)
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print("\t(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}", file=config)
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print("};", file=config)
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def gen_pci_hide(config):
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"""Generate hide pci information for this platform"""
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if board_cfg_lib.BOARD_NAME in list(board_cfg_lib.KNOWN_HIDDEN_PDEVS_BOARD_DB.keys()) and board_cfg_lib.KNOWN_HIDDEN_PDEVS_BOARD_DB[board_cfg_lib.BOARD_NAME] != 0:
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hidden_pdev_list = board_cfg_lib.KNOWN_HIDDEN_PDEVS_BOARD_DB[board_cfg_lib.BOARD_NAME]
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hidden_pdev_num = len(hidden_pdev_list)
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print("const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM] = {", file=config)
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for hidden_pdev_i in range(hidden_pdev_num):
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bus = hex(int(hidden_pdev_list[hidden_pdev_i].split(':')[0], 16))
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dev = hex(int(hidden_pdev_list[hidden_pdev_i].split(':')[1], 16))
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fun = hex(int(hidden_pdev_list[hidden_pdev_i].split(':')[2], 16))
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print("\t{", file=config)
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print("\t\t.bits.b = {}U,".format(bus), file=config)
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print("\t\t.bits.d = {}U,".format(dev), file=config)
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print("\t\t.bits.f = {}U,".format(fun), file=config)
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print("\t},", file=config)
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print("};", file=config)
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else:
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print("const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];", file=config)
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def gen_known_caps_pci_devs(config):
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"""Generate information for known capabilities of pci devices"""
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known_caps_pci_devs = board_cfg_lib.get_known_caps_pci_devs()
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for dev,bdf_list in known_caps_pci_devs.items():
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if dev == "VMSIX":
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print("", file=config)
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bdf_list_len = len(bdf_list)
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if bdf_list_len == 0:
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print("const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];", file=config)
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break
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for i in range(bdf_list_len):
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b = bdf_list[i].split(":")[0]
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d = bdf_list[i].split(":")[1].split(".")[0]
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f = bdf_list[i].split(".")[1]
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print("#define VMSIX_ON_MSI_DEV{}\t.bdf.bits = {{.b = 0x{}U, .d = 0x{}U, .f =0x{}U}},".format(i, b, d, f), file=config)
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for i in range(bdf_list_len):
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if i == 0:
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print("const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM] = {", file=config)
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print("\t{{VMSIX_ON_MSI_DEV{}}},".format(i), file=config)
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if i == (bdf_list_len - 1):
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print("};", file=config)
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def generate_file(config):
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"""
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Start to generate board.c
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:param config: it is a file pointer of board information for writing to
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"""
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err_dic = {}
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print("{0}".format(board_cfg_lib.HEADER_LICENSE), file=config)
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# insert bios info into board.c
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board_cfg_lib.handle_bios_info(config)
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print(INCLUDE_HEADER, file=config)
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# start to parse DMAR info
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gen_dmar_structure(config)
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# start to parse RDT resource info
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err_dic = gen_rdt_res(config)
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if err_dic:
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return err_dic
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# start to parse PX/CX info
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gen_px_cx(config)
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# gen hide pci info for platform
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gen_pci_hide(config)
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# gen known caps of pci dev info for platform
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gen_known_caps_pci_devs(config)
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return err_dic
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