171 lines
7.7 KiB
Plaintext
171 lines
7.7 KiB
Plaintext
/*
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* Intel ACPI Component Architecture
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* AML/ASL+ Disassembler version 20190703 (64-bit version)
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* Copyright (c) 2000 - 2019 Intel Corporation
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*
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* ACPI Data Table [FACP]
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*
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* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
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*/
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[0004] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
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[0004] Table Length : 0000010C
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[0001] Revision : 05
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[0001] Checksum : 00
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[0006] Oem ID : "ACRN "
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[0008] Oem Table ID : "ACRNFADT"
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[0004] Oem Revision : 00000001
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[0004] Asl Compiler ID : "INTL"
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[0004] Asl Compiler Revision : 20190703
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[0004] FACS Address : 00000000
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[0004] DSDT Address : 000F3400
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[0001] Model : 00
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[0001] PM Profile : 00 [Unspecified]
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[0002] SCI Interrupt : 0000
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[0004] SMI Command Port : 00000000
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[0001] ACPI Enable Value : 00
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[0001] ACPI Disable Value : 00
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[0001] S4BIOS Command : 00
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[0001] P-State Control : 00
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[0004] PM1A Event Block Address : 00000000
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[0004] PM1B Event Block Address : 00000000
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[0004] PM1A Control Block Address : 00000000
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[0004] PM1B Control Block Address : 00000000
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[0004] PM2 Control Block Address : 00000000
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[0004] PM Timer Block Address : 00000000
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[0004] GPE0 Block Address : 00000000
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[0004] GPE1 Block Address : 00000000
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[0001] PM1 Event Block Length : 00
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[0001] PM1 Control Block Length : 00
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[0001] PM2 Control Block Length : 00
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[0001] PM Timer Block Length : 00
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[0001] GPE0 Block Length : 00
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[0001] GPE1 Block Length : 00
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[0001] GPE1 Base Offset : 00
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[0001] _CST Support : 00
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[0002] C2 Latency : 0000
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[0002] C3 Latency : 0000
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[0002] CPU Cache Size : 0000
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[0002] Cache Flush Stride : 0000
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[0001] Duty Cycle Offset : 00
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[0001] Duty Cycle Width : 00
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[0001] RTC Day Alarm Index : 00
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[0001] RTC Month Alarm Index : 00
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[0001] RTC Century Index : 00
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[0002] Boot Flags (decoded below) : 0000
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Legacy Devices Supported (V2) : 0
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8042 Present on ports 60/64 (V2) : 0
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VGA Not Present (V4) : 0
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MSI Not Supported (V4) : 0
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PCIe ASPM Not Supported (V4) : 0
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CMOS RTC Not Present (V5) : 0
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[0001] Reserved : 00
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[0004] Flags (decoded below) : 00000000
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WBINVD instruction is operational (V1) : 1
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WBINVD flushes all caches (V1) : 0
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All CPUs support C1 (V1) : 1
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C2 works on MP system (V1) : 0
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Control Method Power Button (V1) : 0
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Control Method Sleep Button (V1) : 0
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RTC wake not in fixed reg space (V1) : 0
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RTC can wake system from S4 (V1) : 0
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32-bit PM Timer (V1) : 1
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Docking Supported (V1) : 0
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Reset Register Supported (V2) : 1
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Sealed Case (V3) : 0
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Headless - No Video (V3) : 1
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Use native instr after SLP_TYPx (V3) : 0
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PCIEXP_WAK Bits Supported (V4) : 0
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Use Platform Timer (V4) : 0
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RTC_STS valid on S4 wake (V4) : 0
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Remote Power-on capable (V4) : 0
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Use APIC Cluster Model (V4) : 0
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Use APIC Physical Destination Mode (V4) : 0
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Hardware Reduced (V5) : 1
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Low Power S0 Idle (V5) : 0
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[0012] Reset Register : [Generic Address Structure]
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[0001] Space ID : 01 [SystemIO]
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[0001] Bit Width : 08
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 01 [Byte Access:8]
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[0008] Address : 0000000000000CF9
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[0001] Value to cause reset : 0E
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[0002] ARM Flags (decoded below) : 0000
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PSCI Compliant : 0
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Must use HVC for PSCI : 0
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[0001] FADT Minor Revision : 00
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[0008] FACS Address : 0000000000000000
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[0008] DSDT Address : 0000000000000000
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[0012] PM1A Event Block : [Generic Address Structure]
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[0001] Space ID : 00 [SystemMemory]
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[0001] Bit Width : 00
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 00 [Undefined/Legacy]
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[0008] Address : 0000000000000000
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[0012] PM1B Event Block : [Generic Address Structure]
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[0001] Space ID : 00 [SystemMemory]
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[0001] Bit Width : 00
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 00 [Undefined/Legacy]
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[0008] Address : 0000000000000000
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[0012] PM1A Control Block : [Generic Address Structure]
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[0001] Space ID : 00 [SystemMemory]
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[0001] Bit Width : 00
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 00 [Undefined/Legacy]
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[0008] Address : 0000000000000000
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[0012] PM1B Control Block : [Generic Address Structure]
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[0001] Space ID : 00 [SystemMemory]
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[0001] Bit Width : 00
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 00 [Undefined/Legacy]
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[0008] Address : 0000000000000000
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[0012] PM2 Control Block : [Generic Address Structure]
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[0001] Space ID : 00 [SystemMemory]
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[0001] Bit Width : 00
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 00 [Undefined/Legacy]
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[0008] Address : 0000000000000000
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[0012] PM Timer Block : [Generic Address Structure]
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[0001] Space ID : 00 [SystemMemory]
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[0001] Bit Width : 00
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 00 [Undefined/Legacy]
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[0008] Address : 0000000000000000
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[0012] GPE0 Block : [Generic Address Structure]
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[0001] Space ID : 00 [SystemMemory]
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[0001] Bit Width : 00
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 00 [Undefined/Legacy]
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[0008] Address : 0000000000000000
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[0012] GPE1 Block : [Generic Address Structure]
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[0001] Space ID : 00 [SystemMemory]
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[0001] Bit Width : 00
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 00 [Undefined/Legacy]
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[0008] Address : 0000000000000000
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[0012] Sleep Control Register : [Generic Address Structure]
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[0001] Space ID : 01 [SystemIO]
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[0001] Bit Width : 08
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 01 [Byte Access:8]
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[0008] Address : 0000000000000400
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[0012] Sleep Status Register : [Generic Address Structure]
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[0001] Space ID : 01 [SystemIO]
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[0001] Bit Width : 08
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[0001] Bit Offset : 00
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[0001] Encoded Access Width : 01 [Byte Access:8]
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[0008] Address : 0000000000000401
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