212 lines
4.5 KiB
C
212 lines
4.5 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#define NUM_USER_VMS 2U
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/**********************/
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/* VIRTUAL MACHINE 0 */
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/*********************/
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/* Number of CPUs in this VM*/
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#define VM1_NUM_CPUS 2U
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/* Logical CPU IDs assigned to this VM */
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uint16_t VM1_CPUS[VM1_NUM_CPUS] = {0U, 2U};
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/*********************/
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/* VIRTUAL MACHINE 1 */
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/*********************/
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/* Number of CPUs in this VM*/
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#define VM2_NUM_CPUS 2U
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/* Logical CPU IDs assigned with this VM */
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uint16_t VM2_CPUS[VM2_NUM_CPUS] = {3U, 1U};
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static struct vpci_vdev_array vpci_vdev_array1 = {
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.num_pci_vdev = 2,
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.vpci_vdev_list = {
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{/*vdev 0: hostbridge */
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.vbdf = PCI_BDF(0x00U, 0x00U, 0x00U),
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.ops = &pci_ops_vdev_hostbridge,
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.bar = {}, /* don't care for hostbridge */
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.pdev = {} /* don't care for hostbridge */
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},
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{/*vdev 1*/
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.vbdf = PCI_BDF(0x00U, 0x01U, 0x00U),
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.ops = &pci_ops_vdev_pt,
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.bar = {
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[0] = {
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.base = 0UL,
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.size = ALIGN_UP_4K(0x100UL),
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.type = PCIM_BAR_MEM_32
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},
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[5] = {
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.base = 0UL,
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.size = ALIGN_UP_4K(0x2000UL),
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.type = PCIM_BAR_MEM_32
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},
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},
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.pdev = {
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.bdf = PCI_BDF(0x00U, 0x01U, 0x00U),
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.bar = {
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[0] = {
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.base = 0xa9000000UL,
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.size = 0x100UL,
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.type = PCIM_BAR_MEM_32
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},
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[5] = {
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.base = 0x1a0000000UL,
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.size = 0x2000UL,
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.type = PCIM_BAR_MEM_64
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},
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}
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}
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},
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}
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};
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static struct vpci_vdev_array vpci_vdev_array2 = {
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.num_pci_vdev = 2,
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.vpci_vdev_list = {
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{/*vdev 0: hostbridge*/
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.vbdf = PCI_BDF(0x00U, 0x00U, 0x00U),
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.ops = &pci_ops_vdev_hostbridge,
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.bar = {}, /* don't care for hostbridge */
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.pdev = {} /* don't care for hostbridge */
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},
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{/*vdev 1*/
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.vbdf = PCI_BDF(0x00U, 0x01U, 0x00U),
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.ops = &pci_ops_vdev_pt,
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.bar = {
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[0] = {
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.base = 0UL,
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.size = ALIGN_UP_4K(0x100UL),
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.type = PCIM_BAR_MEM_32
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},
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[5] = {
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.base = 0UL,
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.size = ALIGN_UP_4K(0x2000UL),
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.type = PCIM_BAR_MEM_32
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},
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},
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.pdev = {
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.bdf = PCI_BDF(0x00U, 0x02U, 0x00U),
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.bar = {
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[0] = {
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.base = 0xa8000000UL,
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.size = 0x100UL,
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.type = PCIM_BAR_MEM_32
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},
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[5] = {
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.base = 0x1b0000000UL,
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.size = 0x2000UL,
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.type = PCIM_BAR_MEM_64
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},
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}
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}
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},
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}
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};
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/*******************************/
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/* User Defined VM definitions */
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/*******************************/
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const struct vm_description_array vm_desc_partition = {
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/* Number of user virtual machines */
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.num_vm_desc = NUM_USER_VMS,
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/* Virtual Machine descriptions */
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.vm_desc_array = {
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{
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/* Internal variable, MUSTBE init to -1 */
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.vm_hw_num_cores = VM1_NUM_CPUS,
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.vm_pcpu_ids = &VM1_CPUS[0],
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.vm_id = 1U,
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.start_hpa = 0x100000000UL,
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.mem_size = 0x20000000UL, /* uses contiguous memory from host */
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.vm_vuart = true,
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.bootargs = "root=/dev/sda rw rootwait noxsave maxcpus=2 nohpet console=hvc0 \
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console=ttyS0 no_timer_check ignore_loglevel log_buf_len=16M \
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consoleblank=0 tsc=reliable",
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.vpci_vdev_array = &vpci_vdev_array1,
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.mptable = &mptable_vm1,
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},
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{
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/* Internal variable, MUSTBE init to -1 */
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.vm_hw_num_cores = VM2_NUM_CPUS,
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.vm_pcpu_ids = &VM2_CPUS[0],
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.vm_id = 2U,
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.start_hpa = 0x120000000UL,
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.mem_size = 0x20000000UL, /* uses contiguous memory from host */
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.vm_vuart = true,
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.bootargs = "root=/dev/sda rw rootwait noxsave maxcpus=2 nohpet console=hvc0 \
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console=ttyS0 no_timer_check ignore_loglevel log_buf_len=16M \
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consoleblank=0 tsc=reliable",
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.vpci_vdev_array = &vpci_vdev_array2,
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.mptable = &mptable_vm2,
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},
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}
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};
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const struct pcpu_vm_desc_mapping pcpu_vm_desc_map[] = {
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{
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.vm_desc_ptr = &vm_desc_partition.vm_desc_array[0],
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.is_bsp = true,
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},
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{
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.vm_desc_ptr = &vm_desc_partition.vm_desc_array[1],
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.is_bsp = false,
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},
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{
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.vm_desc_ptr = &vm_desc_partition.vm_desc_array[0],
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.is_bsp = false,
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},
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{
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.vm_desc_ptr = &vm_desc_partition.vm_desc_array[1],
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.is_bsp = true,
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},
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};
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const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
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{ /* 0 to mptable */
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.baseaddr = 0x0U,
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.length = 0xEFFFFU,
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.type = E820_TYPE_RAM
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},
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{ /* mptable 65536U */
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.baseaddr = 0xF0000U,
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.length = 0x10000U,
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.type = E820_TYPE_RESERVED
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},
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{ /* mptable to lowmem */
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.baseaddr = 0x100000U,
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.length = 0x1FF00000U,
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.type = E820_TYPE_RAM
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},
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{ /* lowmem to PCI hole */
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.baseaddr = 0x20000000U,
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.length = 0xa0000000U,
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.type = E820_TYPE_RESERVED
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},
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{ /* PCI hole to 4G */
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.baseaddr = 0xe0000000U,
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.length = 0x20000000U,
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.type = E820_TYPE_RESERVED
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},
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};
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