261 lines
6.7 KiB
C
261 lines
6.7 KiB
C
/*
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* Copyright (C) <2018> Intel Corporation
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#ifdef CONFIG_MTRR_ENABLED
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#define MTRR_FIXED_RANGE_ALL_WB (MTRR_MEM_TYPE_WB \
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| (MTRR_MEM_TYPE_WB << 8U) \
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| (MTRR_MEM_TYPE_WB << 16U) \
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| (MTRR_MEM_TYPE_WB << 24U) \
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| (MTRR_MEM_TYPE_WB << 32U) \
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| (MTRR_MEM_TYPE_WB << 40U) \
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| (MTRR_MEM_TYPE_WB << 48U) \
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| (MTRR_MEM_TYPE_WB << 56U))
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struct fixed_range_mtrr_maps {
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uint32_t msr;
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uint32_t start;
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uint32_t sub_range_size;
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};
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#define MAX_FIXED_RANGE_ADDR 0x100000UL
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#define FIXED_MTRR_INVALID_INDEX -1U
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static struct fixed_range_mtrr_maps fixed_mtrr_map[FIXED_RANGE_MTRR_NUM] = {
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{ MSR_IA32_MTRR_FIX64K_00000, 0x0U, 0x10000U },
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{ MSR_IA32_MTRR_FIX16K_80000, 0x80000U, 0x4000U },
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{ MSR_IA32_MTRR_FIX16K_A0000, 0xA0000U, 0x4000U },
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{ MSR_IA32_MTRR_FIX4K_C0000, 0xC0000U, 0x1000U },
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{ MSR_IA32_MTRR_FIX4K_C8000, 0xC8000U, 0x1000U },
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{ MSR_IA32_MTRR_FIX4K_D0000, 0xD0000U, 0x1000U },
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{ MSR_IA32_MTRR_FIX4K_D8000, 0xD8000U, 0x1000U },
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{ MSR_IA32_MTRR_FIX4K_E0000, 0xE0000U, 0x1000U },
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{ MSR_IA32_MTRR_FIX4K_E8000, 0xE8000U, 0x1000U },
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{ MSR_IA32_MTRR_FIX4K_F0000, 0xF0000U, 0x1000U },
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{ MSR_IA32_MTRR_FIX4K_F8000, 0xF8000U, 0x1000U },
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};
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static uint32_t get_index_of_fixed_mtrr(uint32_t msr)
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{
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uint32_t i;
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for (i = 0U; i < FIXED_RANGE_MTRR_NUM; i++) {
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if (fixed_mtrr_map[i].msr == msr) {
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return i;
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}
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}
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return FIXED_MTRR_INVALID_INDEX;
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}
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static uint32_t
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get_subrange_size_of_fixed_mtrr(uint32_t subrange_id)
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{
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return fixed_mtrr_map[subrange_id].sub_range_size;
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}
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static uint32_t
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get_subrange_start_of_fixed_mtrr(uint32_t index, uint32_t subrange_id)
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{
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return (fixed_mtrr_map[index].start + subrange_id *
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get_subrange_size_of_fixed_mtrr(index));
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}
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static inline bool is_mtrr_enabled(struct vcpu *vcpu)
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{
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return vcpu->mtrr.def_type.bits.enable;
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}
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static inline bool is_fixed_range_mtrr_enabled(struct vcpu *vcpu)
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{
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return ((vcpu->mtrr.cap.bits.fix != 0U) &&
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(vcpu->mtrr.def_type.bits.fixed_enable != 0U));
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}
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static inline uint8_t get_default_memory_type(struct vcpu *vcpu)
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{
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return (uint8_t)(vcpu->mtrr.def_type.bits.type);
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}
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void init_mtrr(struct vcpu *vcpu)
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{
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union mtrr_cap_reg cap = {0};
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uint32_t i;
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/*
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* We emulate fixed range MTRRs only
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* And expecting the guests won't write variable MTRRs
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* since MTRRCap.vcnt is 0
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*/
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vcpu->mtrr.cap.bits.vcnt = 0U;
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vcpu->mtrr.cap.bits.fix = 1U;
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vcpu->mtrr.def_type.bits.enable = 1U;
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vcpu->mtrr.def_type.bits.fixed_enable = 1U;
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vcpu->mtrr.def_type.bits.type = MTRR_MEM_TYPE_UC;
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if (is_vm0(vcpu->vm))
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cap.value = msr_read(MSR_IA32_MTRR_CAP);
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for (i = 0U; i < FIXED_RANGE_MTRR_NUM; i++) {
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if (cap.bits.fix != 0U) {
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/*
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* The system firmware runs in VMX non-root mode on VM0.
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* In some cases, the firmware needs particular mem type
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* at certain mmeory locations (e.g. UC for some
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* hardware registers), so we need to configure EPT
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* according to the content of physical MTRRs.
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*/
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vcpu->mtrr.fixed_range[i].value =
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msr_read(fixed_mtrr_map[i].msr);
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} else {
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/*
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* For non-vm0 EPT, all memory is setup with WB type in
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* EPT, so we setup fixed range MTRRs accordingly.
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*/
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vcpu->mtrr.fixed_range[i].value =
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MTRR_FIXED_RANGE_ALL_WB;
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}
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pr_dbg("vm%d vcpu%hu fixed-range MTRR[%u]: %16llx",
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vcpu->vm->vm_id, vcpu->vcpu_id, i,
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vcpu->mtrr.fixed_range[i].value);
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}
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}
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static uint32_t update_ept(struct vm *vm, uint64_t start,
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uint64_t size, uint8_t type)
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{
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uint64_t attr;
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switch ((uint64_t)type) {
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case MTRR_MEM_TYPE_WC:
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attr = EPT_WC;
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break;
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case MTRR_MEM_TYPE_WT:
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attr = EPT_WT;
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break;
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case MTRR_MEM_TYPE_WP:
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attr = EPT_WP;
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break;
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case MTRR_MEM_TYPE_WB:
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attr = EPT_WB;
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break;
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case MTRR_MEM_TYPE_UC:
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default:
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attr = EPT_UNCACHED;
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break;
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}
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ept_mr_modify(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
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start, size, attr, EPT_MT_MASK);
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return attr;
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}
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static void update_ept_mem_type(struct vcpu *vcpu)
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{
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uint8_t type;
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uint64_t start, size;
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uint32_t i, j;
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/*
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* Intel SDM, Vol 3, 11.11.2.1 Section "IA32_MTRR_DEF_TYPE MSR":
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* - when def_type.E is clear, UC memory type is applied
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* - when def_type.FE is clear, MTRRdefType.type is applied
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*/
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if (!is_mtrr_enabled(vcpu) || !is_fixed_range_mtrr_enabled(vcpu)) {
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update_ept(vcpu->vm, 0U, MAX_FIXED_RANGE_ADDR,
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get_default_memory_type(vcpu));
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return;
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}
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/* Deal with fixed-range MTRRs only */
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for (i = 0U; i < FIXED_RANGE_MTRR_NUM; i++) {
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type = vcpu->mtrr.fixed_range[i].type[0];
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start = get_subrange_start_of_fixed_mtrr(i, 0U);
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size = get_subrange_size_of_fixed_mtrr(i);
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for (j = 1U; j < MTRR_SUB_RANGE_NUM; j++) {
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/* If it's same type, combine the subrange together */
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if (type == vcpu->mtrr.fixed_range[i].type[j]) {
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size += get_subrange_size_of_fixed_mtrr(i);
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} else {
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update_ept(vcpu->vm, start, size, type);
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type = vcpu->mtrr.fixed_range[i].type[j];
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start = get_subrange_start_of_fixed_mtrr(i, j);
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size = get_subrange_size_of_fixed_mtrr(i);
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}
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}
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update_ept(vcpu->vm, start, size, type);
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}
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}
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void mtrr_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t value)
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{
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uint32_t index;
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if (msr == MSR_IA32_MTRR_DEF_TYPE) {
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if (vcpu->mtrr.def_type.value != value) {
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vcpu->mtrr.def_type.value = value;
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/*
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* Guests follow this guide line to update MTRRs:
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* Intel SDM, Volume 3, 11.11.8 Section "MTRR
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* Considerations in MP Systems"
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* 1. Broadcast to all processors
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* 2. Disable Interrupts
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* 3. Wait for all procs to do so
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* 4. Enter no-fill cache mode (CR0.CD=1, CR0.NW=0)
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* 5. Flush caches
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* 6. Clear CR4.PGE bit
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* 7. Flush all TLBs
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* 8. Disable all range registers by MTRRdefType.E
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* 9. Update the MTRRs
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* 10. Enable all range registers by MTRRdeftype.E
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* 11. Flush all TLBs and caches again
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* 12. Enter normal cache mode to re-enable caching
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* 13. Set CR4.PGE
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* 14. Wait for all processors to reach this point
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* 15. Enable interrupts.
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*
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* we don't have to update EPT in step 9
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* but in step 8 and 10 only
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*/
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update_ept_mem_type(vcpu);
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}
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} else {
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index = get_index_of_fixed_mtrr(msr);
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if (index != FIXED_MTRR_INVALID_INDEX) {
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vcpu->mtrr.fixed_range[index].value = value;
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} else {
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pr_err("Write to unexpected MSR: 0x%x", msr);
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}
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}
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}
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uint64_t mtrr_rdmsr(struct vcpu *vcpu, uint32_t msr)
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{
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struct mtrr_state *mtrr = &vcpu->mtrr;
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uint64_t ret = 0UL;
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uint32_t index;
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if (msr == MSR_IA32_MTRR_CAP) {
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ret = mtrr->cap.value;
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} else if (msr == MSR_IA32_MTRR_DEF_TYPE) {
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ret = mtrr->def_type.value;
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} else {
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index = get_index_of_fixed_mtrr(msr);
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if (index != FIXED_MTRR_INVALID_INDEX) {
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ret = mtrr->fixed_range[index].value;
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} else {
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pr_err("read unexpected MSR: 0x%x", msr);
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}
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}
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return ret;
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}
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#endif /* CONFIG_MTRR_ENABLED */
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