149 lines
3.2 KiB
C
149 lines
3.2 KiB
C
/*
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* Copyright (C) 2020-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <asm/cpu.h>
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#include <asm/cpu_caps.h>
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#include <asm/cpufeatures.h>
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#include <asm/cpuid.h>
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#include <errno.h>
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#include <logmsg.h>
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#include <asm/rdt.h>
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#include <asm/lib/bits.h>
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#include <asm/board.h>
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#include <asm/vm_config.h>
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#include <asm/msr.h>
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const uint16_t hv_clos = 0U;
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/* RDT features can support different numbers of CLOS. Set the lowest numerical
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* clos value (common_num_closids - 1) that is common between the resources as
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* each resource's clos max value to have consistent allocation.
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*/
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#ifdef CONFIG_RDT_ENABLED
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/*
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* @pre res == RDT_RESOURCE_L3 || res == RDT_RESOURCE_L2 || res == RDT_RESOURCE_MBA
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*/
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const struct rdt_ins *get_rdt_res_ins(int res, uint16_t pcpu_id)
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{
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uint32_t i;
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struct rdt_type *info = &res_cap_info[res];
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struct rdt_ins *ins = NULL;
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for (i = 0U; i < info->num_ins; i++) {
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if (bitmap_test(pcpu_id, &info->ins_array[i].cpu_mask)) {
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ins = &info->ins_array[i];
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break;
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}
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}
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return ins;
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}
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static void setup_res_clos_msr(uint16_t pcpu_id, struct rdt_type *info, struct rdt_ins *ins)
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{
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uint16_t i;
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uint32_t msr_index;
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uint64_t val = 0;
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uint32_t res = info->res_id;
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union clos_config *cfg = ins->clos_config_array;
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if (res != RDT_RESID_MBA && ins->res.cache.is_cdp_enabled) {
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/* enable CDP before setting COS to simplify CAT mask remapping
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* and prevent unintended behavior.
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*/
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msr_write(info->msr_qos_cfg, 0x1UL);
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}
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for (i = 0U; i < ins->num_clos_config; i++) {
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switch (res) {
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case RDT_RESOURCE_L3:
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case RDT_RESOURCE_L2:
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val = (uint64_t)cfg[i].clos_mask;
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break;
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case RDT_RESOURCE_MBA:
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val = (uint64_t)cfg[i].mba_delay;
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break;
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default:
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ASSERT(res < RDT_NUM_RESOURCES, "Support only 3 RDT resources. res=%d is invalid", res);
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}
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msr_index = info->msr_base + i;
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msr_write_pcpu(msr_index, val, pcpu_id);
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}
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}
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void setup_clos(uint16_t pcpu_id)
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{
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uint16_t i, j;
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struct rdt_type *info;
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struct rdt_ins *ins;
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for (i = 0U; i < RDT_NUM_RESOURCES; i++) {
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info = &res_cap_info[i];
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for (j = 0U; j < info->num_ins; j++) {
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ins = &info->ins_array[j];
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if (bitmap_test(pcpu_id, &ins->cpu_mask)) {
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setup_res_clos_msr(pcpu_id, info, ins);
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}
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}
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}
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/* set hypervisor RDT resource clos */
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msr_write_pcpu(MSR_IA32_PQR_ASSOC, clos2pqr_msr(hv_clos), pcpu_id);
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}
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uint64_t clos2pqr_msr(uint16_t clos)
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{
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uint64_t pqr_assoc;
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pqr_assoc = msr_read(MSR_IA32_PQR_ASSOC);
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pqr_assoc = (pqr_assoc & 0xffffffffUL) | ((uint64_t)clos << 32U);
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return pqr_assoc;
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}
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static bool is_rdt_type_capable(struct rdt_type *info)
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{
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uint32_t i;
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struct rdt_ins *ins;
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bool ret = false;
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if (info->num_ins > 0U) {
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for (i = 0U; i < info->num_ins; i++) {
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ins = &info->ins_array[i];
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if (ins->num_closids > 0U) {
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ret = true;
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break;
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}
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}
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}
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return ret;
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}
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bool is_platform_rdt_capable(void)
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{
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bool ret = false;
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if (is_rdt_type_capable(&res_cap_info[RDT_RESOURCE_L3]) ||
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is_rdt_type_capable(&res_cap_info[RDT_RESOURCE_L2]) ||
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is_rdt_type_capable(&res_cap_info[RDT_RESOURCE_MBA])) {
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ret = true;
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}
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return ret;
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}
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#else
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uint64_t clos2pqr_msr(__unused uint16_t clos)
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{
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return 0UL;
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}
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bool is_platform_rdt_capable(void)
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{
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return false;
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}
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#endif
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