527 lines
12 KiB
C
527 lines
12 KiB
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <errno.h>
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#include <irq.h>
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#include <asm/lib/spinlock.h>
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#include <asm/ioapic.h>
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#include <asm/irq.h>
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#include <asm/pgtable.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <acpi.h>
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#include <logmsg.h>
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#define NR_MAX_GSI (CONFIG_MAX_IOAPIC_NUM * CONFIG_MAX_IOAPIC_LINES)
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#define DEFAULT_DEST_MODE IOAPIC_RTE_DESTMODE_LOGICAL
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#define DEFAULT_DELIVERY_MODE IOAPIC_RTE_DELMODE_LOPRI
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/*
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* is_valid is by default false when all the
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* static variables, part of .bss, are initialized to 0s
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* It is set to true, if the corresponding
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* gsi falls in ranges identified by IOAPIC data
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* in ACPI MADT in ioapic_setup_irqs.
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*/
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struct gsi_table {
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bool is_valid;
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struct {
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uint8_t acpi_id;
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uint8_t index;
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uint32_t pin;
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void *base_addr;
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} ioapic_info;
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};
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static struct gsi_table gsi_table_data[NR_MAX_GSI];
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static uint32_t ioapic_max_nr_gsi;
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static spinlock_t ioapic_lock = { .head = 0U, .tail = 0U, };
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static union ioapic_rte saved_rte[CONFIG_MAX_IOAPIC_NUM][CONFIG_MAX_IOAPIC_LINES];
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static const uint32_t legacy_irq_trigger_mode[NR_LEGACY_PIN] = {
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ2*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ1*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ0*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ3*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ4*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ5*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ6*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ7*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ8*/
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IOAPIC_RTE_TRGRMODE_LEVEL, /* IRQ9*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ10*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ11*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ12*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ13*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ14*/
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IOAPIC_RTE_TRGRMODE_EDGE, /* IRQ15*/
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};
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static const uint32_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
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2U, /* pin0*/
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1U, /* pin1*/
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0U, /* pin2*/
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3U, /* pin3*/
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4U, /* pin4*/
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5U, /* pin5*/
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6U, /* pin6*/
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7U, /* pin7*/
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8U, /* pin8*/
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9U, /* pin9*/
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10U, /* pin10*/
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11U, /* pin11*/
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12U, /* pin12*/
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13U, /* pin13*/
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14U, /* pin14*/
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15U, /* pin15*/
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};
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static struct ioapic_info ioapic_array[CONFIG_MAX_IOAPIC_NUM];
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static uint8_t ioapic_num;
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uint32_t get_pic_pin_from_ioapic_pin(uint32_t pin_index)
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{
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uint32_t pin_id = INVALID_INTERRUPT_PIN;
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if (pin_index < NR_LEGACY_PIN) {
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pin_id = pic_ioapic_pin_map[pin_index];
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}
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return pin_id;
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}
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uint8_t get_platform_ioapic_info (struct ioapic_info **plat_ioapic_info)
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{
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*plat_ioapic_info = ioapic_array;
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return ioapic_num;
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}
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uint8_t get_gsi_to_ioapic_index(uint32_t gsi)
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{
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return gsi_table_data[gsi].ioapic_info.index;
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}
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/*
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* @pre gsi < NR_MAX_GSI
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*/
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void *gsi_to_ioapic_base(uint32_t gsi)
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{
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return gsi_table_data[gsi].ioapic_info.base_addr;
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}
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uint32_t get_max_nr_gsi(void)
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{
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return ioapic_max_nr_gsi;
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}
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static void *map_ioapic(uint64_t ioapic_paddr)
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{
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/* At some point we may need to translate this paddr to a vaddr.
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* 1:1 mapping for now.
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*/
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return hpa2hva(ioapic_paddr);
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}
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static inline uint32_t
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ioapic_read_reg32(void *ioapic_base, const uint32_t offset)
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{
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uint32_t v;
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uint64_t rflags;
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spinlock_irqsave_obtain(&ioapic_lock, &rflags);
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/* Write IOREGSEL */
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mmio_write32(offset, ioapic_base + IOAPIC_REGSEL);
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/* Read IOWIN */
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v = mmio_read32(ioapic_base + IOAPIC_WINDOW);
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spinlock_irqrestore_release(&ioapic_lock, rflags);
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return v;
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}
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static inline void
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ioapic_write_reg32(void *ioapic_base, const uint32_t offset, const uint32_t value)
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{
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uint64_t rflags;
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spinlock_irqsave_obtain(&ioapic_lock, &rflags);
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/* Write IOREGSEL */
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mmio_write32(offset, ioapic_base + IOAPIC_REGSEL);
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/* Write IOWIN */
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mmio_write32(value, ioapic_base + IOAPIC_WINDOW);
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spinlock_irqrestore_release(&ioapic_lock, rflags);
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}
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/**
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* @pre apic_id < 2
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*/
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static inline uint64_t
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get_ioapic_base(uint8_t apic_id)
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{
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/* the ioapic base should be extracted from ACPI MADT table */
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return ioapic_array[apic_id].addr;
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}
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void ioapic_get_rte_entry(void *ioapic_base, uint32_t pin, union ioapic_rte *rte)
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{
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uint32_t rte_addr = (pin * 2U) + 0x10U;
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rte->u.lo_32 = ioapic_read_reg32(ioapic_base, rte_addr);
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rte->u.hi_32 = ioapic_read_reg32(ioapic_base, rte_addr + 1U);
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}
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static inline void
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ioapic_set_rte_entry(void *ioapic_base,
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uint32_t pin, union ioapic_rte rte)
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{
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uint32_t rte_addr = (pin * 2U) + 0x10U;
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ioapic_write_reg32(ioapic_base, rte_addr, rte.u.lo_32);
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ioapic_write_reg32(ioapic_base, rte_addr + 1U, rte.u.hi_32);
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}
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static inline union ioapic_rte
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create_rte_for_legacy_irq(uint32_t irq, uint32_t vr)
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{
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union ioapic_rte rte;
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/* Legacy IRQ 0-15 setup, default masked
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* are actually defined in either MPTable or ACPI MADT table
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* before we have ACPI table parsing in HV we use common hardcode
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*/
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rte.full = 0UL;
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rte.bits.intr_mask = IOAPIC_RTE_MASK_SET;
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rte.bits.trigger_mode = legacy_irq_trigger_mode[irq];
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rte.bits.dest_mode = DEFAULT_DEST_MODE;
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rte.bits.delivery_mode = DEFAULT_DELIVERY_MODE;
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rte.bits.vector = vr;
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/* Fixed to active high */
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rte.bits.intr_polarity = IOAPIC_RTE_INTPOL_AHI;
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/* Dest field: legacy irq fixed to CPU0 */
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rte.bits.dest_field = 1U;
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return rte;
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}
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static inline union ioapic_rte
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create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
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{
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union ioapic_rte rte;
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rte.full = 0UL;
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if (irq < NR_LEGACY_PIN) {
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rte = create_rte_for_legacy_irq(irq, vr);
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} else {
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/* irq default masked, level trig */
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rte.bits.intr_mask = IOAPIC_RTE_MASK_SET;
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rte.bits.trigger_mode = IOAPIC_RTE_TRGRMODE_LEVEL;
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rte.bits.dest_mode = DEFAULT_DEST_MODE;
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rte.bits.delivery_mode = DEFAULT_DELIVERY_MODE;
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rte.bits.vector = vr;
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/* Fixed to active high */
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rte.bits.intr_polarity = IOAPIC_RTE_INTPOL_AHI;
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/* Dest field */
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rte.bits.dest_field = (uint8_t) ALL_CPUS_MASK;
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}
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return rte;
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}
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static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
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{
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void *ioapic_base;
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union ioapic_rte rte;
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ioapic_base = gsi_to_ioapic_base(gsi);
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rte = create_rte_for_gsi_irq(gsi, vr);
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ioapic_set_rte_entry(ioapic_base, gsi_table_data[gsi].ioapic_info.pin, rte);
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if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) {
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set_irq_trigger_mode(gsi, true);
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} else {
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set_irq_trigger_mode(gsi, false);
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}
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dev_dbg(DBG_LEVEL_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
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gsi, gsi_table_data[gsi].ioapic_info.pin,
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rte.full);
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}
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/*
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* @pre rte != NULL
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* @pre is_ioapic_irq(irq) == true
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*/
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void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte)
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{
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void *addr;
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addr = gsi_to_ioapic_base(irq);
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ioapic_get_rte_entry(addr, gsi_table_data[irq].ioapic_info.pin, rte);
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}
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/*
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* @pre is_ioapic_irq(irq) == true
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*/
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void ioapic_set_rte(uint32_t irq, union ioapic_rte rte)
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{
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void *addr;
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addr = gsi_to_ioapic_base(irq);
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ioapic_set_rte_entry(addr, gsi_table_data[irq].ioapic_info.pin, rte);
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dev_dbg(DBG_LEVEL_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
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irq, gsi_table_data[irq].ioapic_info.pin,
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rte.full);
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}
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/*
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* Checks if the gsi is valid
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* 1) gsi < NR_MAX_GSI
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* 2) gsi is valid on the platform according to ACPI MADT info
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*/
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bool is_gsi_valid(uint32_t gsi)
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{
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return (gsi < NR_MAX_GSI) && (gsi_table_data[gsi].is_valid);
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}
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/*
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* IO-APIC gsi and irq are identity mapped in ioapic_setup_irqs
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* So #gsi = #irq for ACRN
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*/
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bool is_ioapic_irq(uint32_t irq)
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{
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return is_gsi_valid(irq);
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}
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/*
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*@pre gsi < NR_MAX_GSI
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*@pre is_gsi_valid(gsi) == true
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*/
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uint32_t gsi_to_ioapic_pin(uint32_t gsi)
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{
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return gsi_table_data[gsi].ioapic_info.pin;
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}
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/*
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*@pre is_gsi_valid(gsi) == true
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*/
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uint32_t ioapic_gsi_to_irq(uint32_t gsi)
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{
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return gsi;
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}
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static void
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ioapic_irq_gsi_mask_unmask(uint32_t irq, bool mask)
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{
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void *addr = NULL;
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uint32_t pin;
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union ioapic_rte rte;
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addr = gsi_to_ioapic_base(irq);
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pin = gsi_table_data[irq].ioapic_info.pin;
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if (addr != NULL) {
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ioapic_get_rte_entry(addr, pin, &rte);
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if (mask) {
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rte.bits.intr_mask = IOAPIC_RTE_MASK_SET;
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} else {
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rte.bits.intr_mask = IOAPIC_RTE_MASK_CLR;
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}
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ioapic_set_rte_entry(addr, pin, rte);
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dev_dbg(DBG_LEVEL_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
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irq, pin, rte.full);
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} else {
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dev_dbg(DBG_LEVEL_PTIRQ, "NULL Address returned from gsi_table_data");
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}
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}
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void ioapic_gsi_mask_irq(uint32_t irq)
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{
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ioapic_irq_gsi_mask_unmask(irq, true);
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}
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void ioapic_gsi_unmask_irq(uint32_t irq)
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{
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ioapic_irq_gsi_mask_unmask(irq, false);
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}
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static uint32_t
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ioapic_nr_pins(void *ioapic_base)
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{
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uint32_t version;
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uint32_t nr_pins;
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version = ioapic_read_reg32(ioapic_base, IOAPIC_VER);
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dev_dbg(DBG_LEVEL_IRQ, "IOAPIC version: %x", version);
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/* The 23:16 bits in the version register is the highest entry in the
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* I/O redirection table, which is 1 smaller than the number of
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* interrupt input pins. */
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nr_pins = (((version & IOAPIC_MAX_RTE_MASK) >> MAX_RTE_SHIFT) + 1U);
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return nr_pins;
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}
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/*
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* @pre is_ioapic_irq(irq) == true
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*/
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uint8_t ioapic_irq_to_ioapic_id(uint32_t irq)
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{
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return gsi_table_data[irq].ioapic_info.acpi_id;
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}
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int32_t init_ioapic_id_info(void)
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{
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int32_t ret = 0;
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uint8_t ioapic_id;
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void *addr;
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uint32_t nr_pins, gsi;
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ioapic_num = parse_madt_ioapic(&ioapic_array[0]);
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if (ioapic_num <= (uint8_t)CONFIG_MAX_IOAPIC_NUM) {
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/*
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* Iterate thru all the IO-APICs on the platform
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* Check the number of pins available on each IOAPIC is less
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* than the CONFIG_MAX_IOAPIC_LINES
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*/
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gsi = 0U;
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for (ioapic_id = 0U; ioapic_id < ioapic_num; ioapic_id++) {
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addr = map_ioapic(ioapic_array[ioapic_id].addr);
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set_paging_supervisor((uint64_t)addr, PAGE_SIZE);
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nr_pins = ioapic_nr_pins(addr);
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if (nr_pins <= (uint32_t) CONFIG_MAX_IOAPIC_LINES) {
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gsi += nr_pins;
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ioapic_array[ioapic_id].nr_pins = nr_pins;
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} else {
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pr_err ("Pin count %x of IOAPIC with %x > CONFIG_MAX_IOAPIC_LINES, bump up CONFIG_MAX_IOAPIC_LINES!",
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nr_pins, ioapic_array[ioapic_id].id);
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ret = -EINVAL;
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break;
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}
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}
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/*
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* Check if total pin count, can be inferred by GSI, is
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* atleast same as the number of Legacy IRQs, NR_LEGACY_IRQ
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*/
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if (ret == 0) {
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if (gsi < (uint32_t) NR_LEGACY_PIN) {
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pr_err ("Total pin count (%x) is less than NR_LEGACY_IRQ!", gsi);
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ret = -EINVAL;
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}
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}
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} else {
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pr_err ("Number of IOAPIC on platform %x > CONFIG_MAX_IOAPIC_NUM, try bumping up CONFIG_MAX_IOAPIC_NUM!",
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ioapic_num);
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ret = -EINVAL;
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}
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return ret;
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}
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void ioapic_setup_irqs(void)
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{
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uint8_t ioapic_id;
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uint32_t gsi = 0U;
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uint32_t vr;
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for (ioapic_id = 0U;
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ioapic_id < ioapic_num; ioapic_id++) {
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void *addr;
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uint32_t pin, nr_pins;
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addr = map_ioapic(ioapic_array[ioapic_id].addr);
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nr_pins = ioapic_array[ioapic_id].nr_pins;
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gsi = ioapic_array[ioapic_id].gsi_base;
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for (pin = 0U; pin < nr_pins; pin++) {
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gsi_table_data[gsi].is_valid = true;
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gsi_table_data[gsi].ioapic_info.acpi_id = ioapic_array[ioapic_id].id;
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gsi_table_data[gsi].ioapic_info.base_addr = addr;
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gsi_table_data[gsi].ioapic_info.pin = pin;
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gsi_table_data[gsi].ioapic_info.index = ioapic_id;
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/* pinned irq before use it */
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if (reserve_irq_num(gsi) == IRQ_INVALID) {
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pr_err("failed to alloc IRQ[%d]", gsi);
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gsi++;
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continue;
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}
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/* assign vector for this GSI
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* for legacy irq, reserved vector and never free
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*/
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if (gsi < NR_LEGACY_PIN) {
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vr = alloc_irq_vector(gsi);
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if (vr == VECTOR_INVALID) {
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pr_err("failed to alloc VR");
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gsi++;
|
|
continue;
|
|
}
|
|
} else {
|
|
vr = 0U; /* not to allocate VR right now */
|
|
}
|
|
|
|
ioapic_set_routing(gsi, vr);
|
|
gsi++;
|
|
}
|
|
}
|
|
|
|
/* system max gsi numbers */
|
|
ioapic_max_nr_gsi = gsi;
|
|
}
|
|
|
|
void suspend_ioapic(void)
|
|
{
|
|
uint8_t ioapic_id;
|
|
uint32_t ioapic_pin;
|
|
|
|
for (ioapic_id = 0U; ioapic_id < ioapic_num; ioapic_id++) {
|
|
void *addr;
|
|
|
|
addr = map_ioapic(get_ioapic_base(ioapic_id));
|
|
for (ioapic_pin = 0U; ioapic_pin < ioapic_array[ioapic_id].nr_pins; ioapic_pin++) {
|
|
ioapic_get_rte_entry(addr, ioapic_pin,
|
|
&saved_rte[ioapic_id][ioapic_pin]);
|
|
}
|
|
}
|
|
}
|
|
|
|
void resume_ioapic(void)
|
|
{
|
|
uint8_t ioapic_id;
|
|
uint32_t ioapic_pin;
|
|
|
|
for (ioapic_id = 0U; ioapic_id < ioapic_num; ioapic_id++) {
|
|
void *addr;
|
|
|
|
addr = map_ioapic(get_ioapic_base(ioapic_id));
|
|
for (ioapic_pin = 0U; ioapic_pin < ioapic_array[ioapic_id].nr_pins; ioapic_pin++) {
|
|
ioapic_set_rte_entry(addr, ioapic_pin,
|
|
saved_rte[ioapic_id][ioapic_pin]);
|
|
}
|
|
}
|
|
}
|