92 lines
1.8 KiB
C
92 lines
1.8 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm.h>
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#include <io.h>
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#define CMOS_ADDR_PORT 0x70U
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#define CMOS_DATA_PORT 0x71U
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#define RTC_STATUSA 0x0AU /* status register A */
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#define RTCSA_TUP 0x80U /* time update, don't look now */
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static spinlock_t cmos_lock = { .head = 0U, .tail = 0U };
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static uint8_t cmos_read(uint8_t addr)
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{
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pio_write8(addr, CMOS_ADDR_PORT);
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return pio_read8(CMOS_DATA_PORT);
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}
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static bool cmos_update_in_progress(void)
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{
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return (cmos_read(RTC_STATUSA) & RTCSA_TUP)?1:0;
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}
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static uint8_t cmos_get_reg_val(uint8_t addr)
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{
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uint8_t reg;
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int32_t tries = 2000;
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spinlock_obtain(&cmos_lock);
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/* Make sure an update isn't in progress */
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while (cmos_update_in_progress() && (tries != 0)) {
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tries -= 1;
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}
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reg = cmos_read(addr);
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spinlock_release(&cmos_lock);
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return reg;
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}
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/**
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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static bool vrtc_read(struct acrn_vcpu *vcpu, uint16_t addr, __unused size_t width)
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{
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uint8_t offset;
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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struct acrn_vm *vm = vcpu->vm;
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offset = vm->vrtc_offset;
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if (addr == CMOS_ADDR_PORT) {
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pio_req->value = vm->vrtc_offset;
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} else {
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pio_req->value = cmos_get_reg_val(offset);
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}
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return true;
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}
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/**
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* @pre vcpu != NULL
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* @pre vcpu->vm != NULL
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*/
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static bool vrtc_write(struct acrn_vcpu *vcpu, uint16_t addr, size_t width,
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uint32_t value)
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{
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if ((width == 1U) && (addr == CMOS_ADDR_PORT)) {
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vcpu->vm->vrtc_offset = (uint8_t)value & 0x7FU;
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}
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return true;
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}
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void vrtc_init(struct acrn_vm *vm)
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{
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struct vm_io_range range = {
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.base = CMOS_ADDR_PORT, .len = 2U};
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/* Initializing the CMOS RAM offset to 0U */
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vm->vrtc_offset = 0U;
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register_pio_emulation_handler(vm, RTC_PIO_IDX, &range, vrtc_read, vrtc_write);
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}
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