151 lines
5.0 KiB
C
151 lines
5.0 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Emulate GPIO registers which are only accessible through Primary to Sideband Bridge (P2SB).
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*
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* Intercept accesses to MISCCFG.GPDMINTSEL[31:24] and PADCFG1.INTSEL[7:0] GPIO registers which hold physical interrupt
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* lines and return virtualized values upon read in accordance with the gsi to vgsi mappings given by the VM config.
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*
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* P2SB_BAR_ADDR: 0xFD000000 (fixed by BIOS)
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*
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*
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* --------------------------------------------------------------------------------------
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* SideBand Endpoint Name | Port ID
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* --------------------------------------------------------------------------------------
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* GPIO Community 5 | 0x69
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* GPIO Community 4 | 0x6A
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* GPIO Community 3 | 0x6B
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* GPIO Community 2 | 0x6C
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* GPIO Community 1 | 0x6D
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* GPIO Community 0 | 0x6E
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* --------------------------------------------------------------------------------------
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*
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* Private Configuration Register (PCR) Address = P2SB_BAR_ADDR + (Port ID << 16) + Register Offset
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* e.g.)
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* GPIO_COMMUNITY_5_PCR_BASE = P2SB_BAR_ADDR + (0x69 << 16) = 0xFD690000
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* GPIO_COMMUNITY_5_MISCCFG = GPIO_COMMUNITY_5_PCR_BASE + 0x010 = 0xFD690010
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* GPIO_COMMUNITY_5_PAD0_CFG1 = GPIO_COMMUNITY_5_PCR_BASE + 0x704 = 0xFD690704
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* GPIO_COMMUNITY_5_PAD1_CFG1 = GPIO_COMMUNITY_5_PCR_BASE + 0x714 = 0xFD690714
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* GPIO_COMMUNITY_5_PAD2_CFG1 = GPIO_COMMUNITY_5_PCR_BASE + 0x724 = 0xFD690724
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* ....
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*
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*/
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#include <types.h>
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#include <errno.h>
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#include <asm/guest/vm.h>
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#include <asm/guest/ept.h>
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#include <asm/guest/assign.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#ifdef P2SB_VGPIO_DM_ENABLED
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#define P2SB_PORTID_SHIFT 16U
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#define P2SB_AGENT_NUM 256U
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#define P2SB_PCR_SPACE_SIZE_PER_AGENT 0x10000U
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#define P2SB_PCR_SPACE_SIZE_TOTAL (P2SB_AGENT_NUM * P2SB_PCR_SPACE_SIZE_PER_AGENT)
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#define P2SB_PCR_SPACE_MASK ((1UL << P2SB_PORTID_SHIFT) - 1UL)
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#define GPIO_MISCCFG 0x010U
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#define GPIO_MISGCFG_GPDMINTSEL_SHIFT 24U
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#define GPIO_PADBAR 0x00CU
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#define GPIO_PADCFG1 0x004U
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#define GPIO_PADCFG1_INTSEL_SHIFT 0U
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#define GPIO_INVALID_PIN 0xFFU
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/**
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* @return vpin mapped to the given phys_pin in accordance with the VM config, if not found return 0xFF as invalid pin
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*/
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static uint32_t ioapic_pin_to_vpin(struct acrn_vm *vm, const struct acrn_vm_config *vm_config, const uint32_t phys_pin)
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{
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uint32_t i;
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uint32_t vpin = GPIO_INVALID_PIN;
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struct acrn_single_vioapic *vioapic;
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for (i = 0U; i < vm_config->pt_intx_num; i++) {
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if (phys_pin == gsi_to_ioapic_pin(vm_config->pt_intx[i].phys_gsi)) {
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vioapic = vgsi_to_vioapic_and_vpin(vm, vm_config->pt_intx[i].virt_gsi, &vpin);
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if (!vioapic) {
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vpin = GPIO_INVALID_PIN;
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}
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break;
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}
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}
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return vpin;
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}
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static int32_t vgpio_mmio_handler(struct io_request *io_req, void *data)
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{
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struct acrn_mmio_request *mmio = &io_req->reqs.mmio_request;
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struct acrn_vm *vm = (struct acrn_vm *) data;
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struct acrn_vm_config *vm_config = get_vm_config(vm->vm_id);
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int32_t ret = 0;
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uint64_t hpa = P2SB_BAR_ADDR + (mmio->address & (uint64_t)(P2SB_PCR_SPACE_SIZE_TOTAL - 1));
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void *hva = hpa2hva(hpa);
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uint64_t reg_offset = hpa & P2SB_PCR_SPACE_MASK;
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uint32_t value, shift;
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uint32_t padbar, pad0;
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uint32_t phys_pin, virt_pin;
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/* all gpio registers have 4 bytes size */
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if (mmio->size == 4U) {
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if (mmio->direction == ACRN_IOREQ_DIR_READ) {
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padbar = mmio_read32((const void *)hpa2hva((hpa & ~P2SB_PCR_SPACE_MASK) + GPIO_PADBAR));
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pad0 = padbar & P2SB_PCR_SPACE_MASK;
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value = mmio_read32((const void *)hva);
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if ((reg_offset == GPIO_MISCCFG) ||
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((reg_offset >= pad0) && ((reg_offset & 0x0FU) == GPIO_PADCFG1))) {
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shift = (reg_offset == GPIO_MISCCFG) ? GPIO_MISGCFG_GPDMINTSEL_SHIFT :
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GPIO_PADCFG1_INTSEL_SHIFT;
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phys_pin = (value >> shift) & 0xFFU;
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virt_pin = ioapic_pin_to_vpin(vm, vm_config, phys_pin);
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value = (value & ~(0xFFU << shift)) | (virt_pin << shift);
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}
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mmio->value = (uint64_t)value;
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} else {
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value = (uint32_t)mmio->value;
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if (reg_offset == GPIO_MISCCFG) { /* discard writes to MISCCFG.GPDMINTSEL[31:24] */
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value = (value & ~(0xFFU << GPIO_MISGCFG_GPDMINTSEL_SHIFT)) |
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(mmio_read32((const void *)hva) & (0xFFU << GPIO_MISGCFG_GPDMINTSEL_SHIFT));
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}
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mmio_write32(value, (void *)hva);
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}
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} else {
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ret = -EINVAL;
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}
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return ret;
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}
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/**
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* @pre vm != NULL && res != NULL
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*/
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void register_vgpio_handler(struct acrn_vm *vm, const struct acrn_mmiores *res)
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{
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uint64_t gpa_start, gpa_end, gpio_pcr_sz;
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uint64_t base_hpa;
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gpa_start = res->user_vm_pa + (P2SB_BASE_GPIO_PORT_ID << P2SB_PORTID_SHIFT);
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gpio_pcr_sz = P2SB_PCR_SPACE_SIZE_PER_AGENT * P2SB_MAX_GPIO_COMMUNITIES;
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gpa_end = gpa_start + gpio_pcr_sz;
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base_hpa = res->host_pa + (P2SB_BASE_GPIO_PORT_ID << P2SB_PORTID_SHIFT);
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/* emulate MMIO access to the GPIO private configuration space registers */
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set_paging_supervisor((uint64_t)hpa2hva(base_hpa), gpio_pcr_sz);
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register_mmio_emulation_handler(vm, vgpio_mmio_handler, gpa_start, gpa_end, (void *)vm, false);
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ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp, gpa_start, gpio_pcr_sz);
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}
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#endif
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