66 lines
1.3 KiB
C
66 lines
1.3 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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/* IOAPIC id */
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#define SBL_IOAPIC_ID 8
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/* IOAPIC base address */
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#define SBL_IOAPIC_ADDR 0xfec00000
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/* IOAPIC range size */
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#define SBL_IOAPIC_SIZE 0x100000
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/* Local APIC base address */
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#define SBL_LAPIC_ADDR 0xfee00000
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/* Local APIC range size */
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#define SBL_LAPIC_SIZE 0x100000
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/* Number of PCI IRQ assignments */
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#define SBL_PCI_IRQ_ASSIGNMENT_NUM 28
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#ifndef CONFIG_DMAR_PARSE_ENABLED
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static struct dmar_dev_scope default_drhd_unit_dev_scope0[] = {
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{ .bus = 0, .devfun = DEVFUN(0x2, 0), },
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};
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static struct dmar_drhd drhd_info_array[] = {
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{
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.dev_cnt = 1,
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.segment = 0,
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.flags = 0,
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.reg_base_addr = 0xFED64000,
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/* Ignore the iommu for intel graphic device since GVT-g needs
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* vtd disabled for gpu
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*/
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.ignore = true,
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.devices = default_drhd_unit_dev_scope0,
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},
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{
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/* No need to specify devices since
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* DRHD_FLAG_INCLUDE_PCI_ALL_MASK set
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*/
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.dev_cnt = 0,
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.segment = 0,
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.flags = DRHD_FLAG_INCLUDE_PCI_ALL_MASK,
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.reg_base_addr = 0xFED65000,
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.ignore = false,
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.devices = NULL,
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},
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};
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static struct dmar_info sbl_dmar_info = {
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.drhd_count = 2,
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.drhd_units = drhd_info_array,
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};
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struct dmar_info *get_dmar_info(void)
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{
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return &sbl_dmar_info;
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}
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#endif
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void init_bsp(void)
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{
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}
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