118 lines
2.5 KiB
C
118 lines
2.5 KiB
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <asm/init.h>
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#include <console.h>
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#include <asm/per_cpu.h>
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#include <shell.h>
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#include <asm/vmx.h>
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#include <asm/guest/vm.h>
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#include <logmsg.h>
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#include <asm/seed.h>
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#include <asm/boot/ld_sym.h>
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#include <boot.h>
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/* boot_regs store the multiboot info magic and address, defined in
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arch/x86/boot/cpu_primary.S.
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*/
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extern uint32_t boot_regs[2];
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/* Push sp magic to top of stack for call trace */
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#define SWITCH_TO(rsp, to) \
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{ \
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asm volatile ("movq %0, %%rsp\n" \
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"pushq %1\n" \
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"jmpq *%2\n" \
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: \
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: "r"(rsp), "rm"(SP_BOTTOM_MAGIC), "a"(to)); \
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}
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/*TODO: move into debug module */
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static void init_debug_pre(void)
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{
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/* Initialize console */
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console_init();
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/* Enable logging */
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init_logmsg();
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}
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/*TODO: move into debug module */
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static void init_debug_post(uint16_t pcpu_id)
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{
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if (pcpu_id == BSP_CPU_ID) {
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/* Initialize the shell */
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shell_init();
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console_setup_timer();
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}
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profiling_setup();
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}
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/*TODO: move into guest-vcpu module */
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static void init_guest_mode(uint16_t pcpu_id)
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{
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vmx_on();
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launch_vms(pcpu_id);
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}
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static void init_pcpu_comm_post(void)
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{
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uint16_t pcpu_id;
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pcpu_id = get_pcpu_id();
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init_pcpu_post(pcpu_id);
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init_debug_post(pcpu_id);
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init_guest_mode(pcpu_id);
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run_idle_thread();
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}
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static void init_misc(void)
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{
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init_cr0_cr4_flexible_bits();
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if (!sanitize_cr0_cr4_pattern()) {
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panic("%s Sanitize pattern of CR0 or CR4 failed.\n", __func__);
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}
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}
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/* NOTE: this function is using temp stack, and after SWITCH_TO(runtime_sp, to)
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* it will switch to runtime stack.
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*/
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void init_primary_pcpu(void)
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{
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uint64_t rsp;
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/* Clear BSS */
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(void)memset(&ld_bss_start, 0U, (size_t)(&ld_bss_end - &ld_bss_start));
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init_acrn_boot_info(boot_regs);
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init_debug_pre();
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if (sanitize_acrn_boot_info(get_acrn_boot_info()) != 0) {
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panic("Sanitize boot info failed!");
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}
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init_pcpu_pre(true);
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init_seed();
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init_misc();
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/* Switch to run-time stack */
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rsp = (uint64_t)(&get_cpu_var(stack)[CONFIG_STACK_SIZE - 1]);
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rsp &= ~(CPU_STACK_ALIGN - 1UL);
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SWITCH_TO(rsp, init_pcpu_comm_post);
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}
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void init_secondary_pcpu(void)
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{
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init_pcpu_pre(false);
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init_pcpu_comm_post();
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}
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