doxygen will warn that documented return type is found for functions
that does not return anything in 1.9.4 or later versions. 'None' is
not a special keyword in doxyge, it will recognize it as description
to the return value that does not exist in void functions.
Tracked-On: #8425
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Currently the DSM (Data of Stolen Memory) size was hardcoded to 64M in
ACRN, meaning that users must set "DVMT Pre-Allocated" to 64M in order
to make IGD passthrough (GVT-d) to work. This patch reads the BIOS-
configured memory size from GGC (GMCH Graphics Control, 0x50) register
and passthrough corresponding area to guest.
Tracked-On: #8432
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Jian Jun Chen <jian.jun.chen@intel.com>
Now the device model only supports the 0..5 PCI bar for PCI/PCIE devices.
This tries to allocate the PCI_MEM32 resource for PCI ROM bar.
V1->V2: Use the PCI_ROMBAR as bar index and PCIBAR_ROM bar type when calling
the pci_emul_alloc_bar to allocate the guest physical addr for PCI ROM bar.
And it will allocate the resource from PCIBAR_MEM32 region.
V2->V3: Add more comments that describes the parameter of pci_emul_alloc_bar.
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
The patch fix many bugs about the pci msi capabilities.
1. Fix the clear msi mask bit issues.
2. Initialize the offset of pci capabilities this variable will used as
the output of pci_emul_find_capability function.
3. Replace 16-read with 32-read because both mask and pending are 32bit.
4. Add mask and pending element in msicap struct and intialize the struct
value to zero, because we need r/w mask and pending value.
Tracked-On: #7762
Signed-off-by: Liu Long <long.liu@linux.intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Rename them to unify the coding style or for simplification
purpose, also remove redundant function declearations
in pci_core.h header file.
v4 update:
SSRAM* -> VSSRAM*
ssram* -> vssram*
Tracked-On: #7010
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
For pass-thru dev PIO bar,ensure it's identical mapping
(guest PIO bar start address equals to host PIO bar start address).
Then in HV side, set the corresponding VMCS io bitmap
to pass-thru these io ports for performance.
Tracked-On: #6508
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
1. refine the name of some functions and struct
2. add the support for PIO bar reservation
Tracked-On: #6508
Signed-off-by: Liu,Junming <junming.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The address of OpRegion is not 4KB aligned,
if the OpRegion + extended VBT size is 16KB,
then it will take up to 5 physical pages in host.
So update the OpRegion size to 20KB
to expose the whole OpRegion to guest.
Tracked-On: #6270
Signed-off-by: Liu,Junming <junming.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
DM maps 64-bit mmio BARs of vdev into 4G-5G, for post-launched VMs. At native
platform, 64-bit MMIO BARs which have 39-bit address, are always mapped into
256G-512G address space.
Change PCI_EMUL_MEMBASE64 to 256G, change PCI_EMUL_MEMLIMIT64 to 512G. So that
the 64-bit vdev BARs of post-launched VMs have same address space with native
platform.
Tracked-On: #5913
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Windows graphic driver obtains DSM address from in-BAR mmio register
which has passthroughed. Not like the other platforms obtained from
pci configure space register which has virtualized. GPU GuC must use
WOPCM in DSM, besides, Windows OS wants to manage DSM also. These two
reason force acrn has to keep identical mapping to avoid trap mmio
BAR to do the emulation.
Tracked-On: #5880
Signed-off-by: Peng Sun <peng.p.sun@intel.com>
GPA base of SW SRAM can't be hardcoded as physical address
of SW SRAM(HPA), as this HPA may vary on different platform.
This patch reserves a dedicated memory slot[GPA: 2G - 8M, 2G)
as SW SRAM region.
Tracked-On: #5649
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
We don't reserve PCI MMIO in e820 Table, it's included in DSDT ACPI Table.
About 0xA0000 - 0x100000 entry, we don't have any ACPI Table touch this region.
So we could remove it too.
After this change, we could only pass the reserved e820 table which we must
reserve to OVMF. In this case, the OVMF could trust ACRN-DM and pass the
reserved e820 table to guest instead of dropping it.
This patch needs the corresponding modify in OVMF. Otherwise, the guest could
not boot.
Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Since this callback is only useful for pass through PCIe device and now pass through
PCIe device emulation has splited from DM to HV. we could remove this callback now.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
The current design has the following problem:
uos kernel may update gvt bars' regions,
but ACRN-DM doesn't know this update.
ACRN-DM only know out-of-date gvt bar regions,
For simplicity, mark these bar regions as OOD bar regions.
uos kernel may allocate OOD bar regions for
other pci devices, which will result in ACRN-DM
bar regions inconsistency with uos kernel.
The new design is the following:
When other pci device update bar regions
(1) ACRN-DM updates gvt bars' regions
provided by a system file.
(2) ACRN-DM updates this pci device bar regions
v5 -> v6:
* add more comments
v4 -> v5:
* remove & for callback func assignment
v3 -> v4:
* compare gpu bar address to avoid unnecessary
* unregistered/registered operation
v2 -> v3:
* call unregister_bar and register_bar when update gvt bars
* update gvt reserved regions when update gvt bars
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The current design has the following problem:
gvt uses some pci bar regions,
but ACRN-DM isn't aware of these regions.
So ACRN-DM may allocate these regions for other pci devices,
which will result in other pci devices bar regions
overlap with gvt bar regions.
The new design is the following:
(1) ACRN-DM reads gvt bar regions
which are provided by physical gpu;
(2) ACRN-DM reserves gvt bar regions
v6 -> v7:
* use array to store reserved bar regions
* rename some struct and func
v5 -> v6:
* rename enable_gvt to gvt_enabled
* add a interface to reserve bar regions
* reserve gvt bar regions
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
PCI spec says that the procedure of sizing a BAR is as follows:
1) disable the decode via command register
2) save the original value of BAR register
3) write all-1 to the BAR register
4) read BAR register back, calculate the size
5) restore the original value to BAR register
6) re-enable the decode via command register
Some driver does not disable the decode of BAR register via the
command register before sizing a BAR. This will lead to a overlay
of the BAR addresses when trying to register the intermediate
BAR address via register_bar. A stateful variable sizing is used
to keep track of such kind of BAR address changes and workaroud
this violation.
Currently this issue is only found when audio device is passed
through to Windows 10 guest. When it is fixed in the Windows
audio driver, this patch should be reverted.
v1 -> v2:
- change the commit message to add the procedure of BAR sizing from
PCI spec
Tracked-On: #2962
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
For PCI passthrough device when guest OS updates the BAR address
the corresponding EPT mapping should be updated as well.
Tracked-On: #2962
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Signed-off-by: Liu Shuo A <shuo.a.liu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
This patch adds support to trigger rescan of virtio-blk device by the
guest VM. This is an alternate to hot-plugging virtio-blk device.
This feature stems from the kata requirement, which hot-plugs container
rootfs after the VM is launched.
As part of virtio-blk rescan,
1. Update the backing file for the virtio-blk device with valid file.
Basically update the empty file (with dummy bctxt) that was passed
during VM launch.
2. Update virtio-blk device configurations for udpated backing file.
3. Update size associated with valid backing file in the config space.
4. Notify guest OS, of the new config change.
5. On this notification, guest will do the following.
(i). Update virtio-blk capacity.
(ii). Revalidate the disk.
(iii). Identify the newly plugged block device.
v5 -> v6:
- Removed use of dummy file and added a new parameter "nodisk"
to virtio-blk which indicates user wants to create a virtio-blk
device with dummy backend.
- Moved vm_monitor_rescan from pci core to virtio-blk as it currently
applies to only virtio-blk.
v4 -> v5:
- Reverted back logic, so that blkrescan is only supported when
VM is launched with empty backend file.
v3 -> v4:
- Close block context before allocating a new one
- Allow backend filepath with additional options to be more generic
- Remove blank lines introduced as part of previous patches.
v2 -> v3:
- Renamed vdev ops vdev_blk rescan to vdev_rescan
- Renamed montior ops virtio_blkrescan_ops to virtio_rescan_ops
- Consolidated virtio-blk configuration specific part into
a separate function
- Removed size requirement in acrnctl command.
v1 -> v2:
- Added more comments in the code.
- Renamed APIs from displug to blkrescan, inline with acrnctl cmd.
- Split the patch into two. This corresponds to changes in acrn-dm.
Tracked-On: #3051
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Guest OS (e.g. Linux) may rely on a gap in E820 map in the 32-bit memory
space to determine the MMIO space for its PCI devices. Leave this gap
when building E820 map to keep the guest's PCI subsystem working.
After commit 7752d5cfe3d11ca0bb9c673ec38bd78ba6578f8e, Linux kernel no
longer requires the MMCONFIG region to be reserved in the E820 map.
Nonetheless, keep it in the reserved region to be on the safe side.
Tracked-On: #2843
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
1G PCI hole is added just after 4G address which is used as the
PCI high MMIO address space. Guest high memory is mapped from 5G
address for both EPT and device model user space address. Guest
e820 table and API vm_map_gpa are updated accordingly.
Tracked-On: #2577
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Replace sscanf in device model hw directory
Tracked-On: #2079
Signed-off-by: Long Liu <long.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: <yonghua.huang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
It is preferred to state the absence of a return value explicitly in the
doxygen-stile comments. Currently there are different styles of doing this,
including:
@return None
@return NULL
@return void
@return N/A
This patch unifies the above with `@return None`.
Tracked-On: #1595
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This function add high level reset_vdev function. Which is
implemented to call deinit/init pairing to emulate the virtual
device reset operation.
This patch also add the system reset which keep the UOS RAM
content functionality to DM.
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
- hardcode the devices' GSI info based on the platform
- reject the passthrough if the following requirement is not met
all the PCI devices that are sharing the same GSI should be assigned
to same VM to avoid physical GSI sharing between multiple VMs.
v4 -> v5
* Move the gsi_dev_mapping_tables definition in a separate file
* Add the GSI info that might be used by GPIO
* Update the HW name
v3 - > v4
* Refine the format of raw data to improve the readability
* Remove the redundant code when adding the new dev into the gsi
sharing group
v2 -> v3
* Add the MSI/MSI-x capability check
Do not add the device which supports MSI/MSI-x to the GSI sharing
group.
v1 -> v2
* Update the GSI raw data based on SBL
* Free the resources when gsi sharing violation occurs
* Move the MACRO PCI_BDF(b, d, f) to pci_core.h since passthrough.c
and gsi_sharing.c are both using it
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Edwin Zhai <edwin.zhai@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
pci_emul_find_capability can be used to get the offset of a PCI
capability in PCI configuration space.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
This reverts commit bc0579d0ff.
The commit bc0579d makes acrn-dm crashed when launch UOS.
Crash log:
./launch_UOS.sh: line 112: 377 Segmentation fault (core dumped) acrn-dm ...
dmesg log:
acrn-dm[1264]: segfault at 1f0 ip 0000000000412257 sp 00007fffc1af9920 error 6 in acrn-dm[400000+3d000]
After this patch reverted, UOS launched successfully.
A couple of problems appeared on Ubuntu 14.04 (gcc 4.8.4) when we
turned on additional compiler flags with commit
519c4285cf104a594776591075ee1c6ee4d61815a. This patch fixes these
problems by adhering to the strict anti-aliasing rules and also
initializing the 'tfd' variable where the compile believed it
_could_ be used uninitialized.
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
We didn't release mmio/io data structure related with PCI bar
of pci dev. Which could trigger memory leak when reboot UOS.
With the new patch, we release the mmio/io data structure
when pci core tries to deinit pci device.
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>
pci_emul_add_capability is needed by virtio 1.0 framework to add
pci vendor capability from outside of pci core.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Jiaqing Zhao