Commit Graph

6 Commits

Author SHA1 Message Date
dongshen 5c32fa610d acrn-config: expose GPIO chassis interrupt to safety VM as INTx
This patch is to expose GPIO chassis interrupts as INTx to safety VM for
EHL. User can configure this per-VM attribute in scenario xml using the
following format:
<pt_intx desc="pt intx mapping.">
  	(phys_gsi0, virt_gsi0), (phys_gsi1, virt_gsi1), (phys_gsiN, virt_gsiN)
 </pt_intx>

The physical and virtual interrupt gsi in each pair are separated by a
comma and enclosed in parentheses. If an integer begins with 0x or 0X,
it is hexadecimal, otherwise, it is assumed to be decimal. Example:
  <pt_intx desc="pt intx mapping.">
  	(1, 0), (0x3, 1), (0x4, 2), (5, 6), (89, 0x12)
  </pt_intx>

Tracked-On: #5241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
2020-09-01 09:35:50 +08:00
dongshen 01c66eb4b3 acrn-config: add support for P2SB bridge passthrough
This patch is to support direct assignment of P2SB bridge to one pre-launched
VM for EHL. User can configure this per-VM attribute in scenario xml:
    <mmio_resources desc="MMIO resources.">
         <p2sb>y</p2sb>
    </mmio_resources>

Set p2sb to y to passthru P2SB bridge to VM, and n otherwise.

Tracked-On: #5221
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
2020-09-01 09:35:50 +08:00
Wei Liu 7eb103478a acrn-config: add MAX_CACHE_CLOS_NUM_ENTRIES/MAX_MBA_CLOS_NUM_ENTRIES macros
1.Add macro MAX_CACHE_CLOS_NUM_ENTRIES for CAT, and MAX_MBA_CLOS_NUM_ENTRIES for MBA.

 MAX_MBA_CLOS_NUM_ENTRIES:
  Max number of Cache Mask entries corresponding to each CLOS.
  This can vary if CDP is enabled vs disabled, as each CLOS entry will have corresponding
  cache mask values for Data and Code when CDP is enabled.

 MAX_CACHE_CLOS_NUM_ENTRIES:
  Max number of MBA delay entries corresponding to each CLOS.

2.Move VMx_VCPU_CLOS macro to misc_cfg.h head file.

Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
2020-08-28 16:44:06 +08:00
dongshen a425730f64 acrn-config: rename MAX_PLATFORM_CLOS_NUM to HV_SUPPORTED_MAX_CLOS
HV_SUPPORTED_MAX_CLOS:
 This value represents the maximum CLOS that is allowed by ACRN hypervisor.
 This value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
 among all supported RDT resources in the platform. In other words, it is
 min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
 CLOS allocations between all the RDT resources.

Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
2020-08-28 16:44:06 +08:00
Wei Liu 01362c3cd1 acrn-config: fix build issue while CDP_ENABLED=y
Fix build issue while CDP_ENABLED=y for EHL-CRB-B.

Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
2020-08-17 14:34:30 +08:00
Wei Liu 6cafb9cf01 acrn-config: configuration source refactor for new layout
Now the hypervisor configuration source code layout is changed, so acrn-config
need to change accordingly to make sure XML based configuration build success;

Tracked-On: #5077
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
2020-07-24 16:16:06 +08:00