previous patch fails to align SUBVID, SUBDID of igd-lpc with physical one.
this patch corrects the errors and refine the code.
Tracked-On: #4405
Signed-off-by: Junming Liu <junming.liu@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
There're some PCI devices need special handler for vendor-specical feature or
capability CFG access. The Intel GPU is one of them. In order to keep the ACRN-HV
clean, we want to throw the qurik part of PCI CFG asccess to DM to handle.
To achieve this, we implement per-device policy base on whether it needs quirk handler
for a VM: each device could configure as "quirk pass through device" or not. For a
"quirk pass through device", we will handle the general part in HV and the quirk part
in DM. For a non "quirk pass through device", we will handle all the part in HV.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
it will send shutdown command to life_mngr on SOS
after the UOS has poweroff itself
Tracked-On: #4446
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
when acrn-dm received shutdown command, it will call this api
to send shutdown command to life_mngr running on SOS via socket.
Tracked-On: #4446
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
it will send "acked" message to UOS if it receives
"shutdown" command from UOS, then wait UOS poweroff itself,
it will send shutdown to life_mngr running on SOS to
shutdown system.
Tracked-On: #4446
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Change shutdown_uos_thread to pm_monitor thread,
the shutdown_uos_thread can do:
--send shutdown request to UOS
--receive acked message from UOS
the pm_monitor can do:
--send shutdown request to UOS
--receive acked message from UOS
--receive shutdown request from UOS
Tracked-On: #4446
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
set the attributes during pm-vuart initialization
to avoid the pm-vuart in an indefinite state.
Currently we have implemented S5 triggered by SOS,
these patch series both support S5 triggered by SOS and RTVM.
the fully steps for S5 triggered by SOS:
1) S5-Trigger: it initiates the platform shutdown actions;
it calls “acrnctl stop vmX” to do that,
and check the VM's status, power-off SOS itself.
2) acrnctl will send “stop” to “acrn-dm”
3) acrn-dm will send “shutdown” command to VMx by v-UART.
4) when life-cycle manager in VMx receives the “shutdown” command,
it will give an “acked” to acrn-dm, and then poweroff itself.
the fully steps for S5 triggered by RTVM:
1) S5-Trigger in RTVM: it initiates the platform shutdown actions;
it’ll send shutdown command for platform shutdown to
life-cycle manager
2) when life-cycle manager in RTVM receive the message,
it will send “shutdown” command to acrn-dm in SOS by v-UART.
3) when acrn-dm receives the “shutdown” command from RTVM,
it will give an “acked” to RTVM, RTVM’s life-cycle manager can
power off itself
4) acrn-dm will send “shutdown” command to its own life-cycle manager
by socket.
5) when life-cycle manager in SOS receives the “shutdown” command,
it can call “s5_trigger” script to shutdown platform.
Tracked-On: #4446
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
In order to add GVT-D support, we need pass through stolen memory and opregion memroy
to the post-launched VM. To implement this, we first reserve the GPA for stolen memory
and opregion memory through post-launched VM e820 table. Then we would build EPT mapping
between the GPA and the stolen memory and opregion memory real HPA. The last, we need to
return the GPA to post-launched VM if it wants to read the stolen memory and opregion
memory address and prevent post-launched VM to write the stolen memory and opregion memory
address register for now.
We do the GPA reserve and GPA to HPA EPT mapping in ACRN-DM and the stolen memory and
opregion memory CFG space register access emulation in ACRN-HV.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Let the ACRN HV to do this in shutdown sequence. In this case, the RTVM could be
still alive if something wrong happened to cause the DM died.
Tracked-On: #4428
Signed-off-by: Li Fei1 <fei1.li@intel.com>
If the guest is RTVM, dm process exit doesn't mean RTVM is
shutdown. Only shutdown_vm in hypervisor guarantee RTVM is
shutodwn. So we should avoid touch guest memory content
from DM if the guest is RTVM.
Tracked-On: #4428
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Since this callback is only useful for pass through PCIe device and now pass through
PCIe device emulation has splited from DM to HV. we could remove this callback now.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
SOS should not access the physical PCI device which is assigned to other guest.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Now we split passthrough PCI device from DM to HV, we could remove all the passthrough
PCI device unused code.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
In this case, we could handle all the passthrough PCI devices in ACRN hypervisor.
But we still need DM to initialize BAR resources and Intx for passthrough PCI
device for post-launched VM since these informations should been filled into
ACPI tables. So
1. we add a HC vm_assign_pcidev to pass the extra informations to replace the old
vm_assign_ptdev.
2. we saso remove HC vm_set_ptdev_msix_info since it could been setted by the post-launched
VM now same as SOS.
3. remove vm_map_ptdev_mmio call for PTDev in DM since ACRN hypervisor will handle these
BAR access.
4. the most important thing is to trap PCI configure space access for PTDev in HV for
post-launched VM and bypass the virtual PCI device configure space access to DM.
This patch doesn't do the clean work. Will do it in the next patch.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Add assign/deassign PCI device ioctl APIs assign a PCI device from SOS to
post-launched VM or deassign a PCI device from post-launched VM to SOS. This patch
is prepared for spliting passthrough PCI device from DM to HV.
The old assign/deassign ptdev APIs will be discarded.
Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Intel Graphics Device(IGD) passthrough on Windows guest
has the restriction that it need a lpc bridge device
located in 00:1f.0 PCI slot.
This patch add a 'gpu' option for 'passthrou' type device,
which will create the dedicated "igd-lpc" for IGD passthrough.
Tracked-On: #4405
v2 -> v3:
* refine the commit message and comments.
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Wu Binbin <binbin.wu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Intel Graphics Device(IGD) passthrough on Windows guest
has the restriction that it need a lpc bridge device
located in 00:1f.0 PCI slot.
This patch add an extra lpc class for this restriction,
the lpc class will be used to create a dummy lpc bridge.
To enable gvt-d GOP driver work,
the VID, DID, REVID, SUBVID, SUBDID of igd-lpc
need aligned with physical one.
Tracked-On: #4405
v2 -> v3:
* refine the comment message and comments.
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Wu Binbin <binbin.wu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
For "Split Device Model", pass-through PCI will be implemented in HV,
"reset" param is added into DM cmdline to ensure PCI device's status before launching VM.
WaaG will fail to boot if adding pass-through audio in default,
because current audio card's reset function isn't supported on WHL platform.
Tracked-On: #4397
Signed-off-by: fangfang.shen <fangfang.shen@intel.com>
uos IGD driver need opregion when enable GVT-d.
This patch pass-thru opregion to uos gpu.
Here is the steps:
(1) set opregion gpa(guest physical addrress) 0xDFFFD000;
(2) get opregion hpa(host physical addrress);
(3) build EPT mapping for opregion.
v1 -> v2:
* initialize the EPT mapping for passthrough GPU opregion region
in passthru_init instead of reading the ASLS config space
v2 -> v3:
* add EPT unmap when deinit
* change some micro name
Tracked-On: #4360
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Wu Binbin <binbin.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
gop driver and uos IGD driver will use
graphics stolen memory(gsm) when enable GVT-d.
This patch pass-thru gsm to uos gpu.
After set physical GPU gsm size 64MB in host BIOS:
Here is the steps:
(1) set gsm gpa(guest physical addrress) 0xDB000000;
(2) get gsm hpa(host physical addrress);
(3) build EPT mapping for gsm.
v1 -> v2:
* initialize the EPT mapping for passthrough GPU gsm region
in passthru_init instead of reading the BDSM config space
v2 -> v3:
* add EPT unmap when deinit
* change some micro name
Tracked-On: #4360
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Wu Binbin <binbin.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Now the PCI bar uses the hardcoded prefetch property
for the pass-through device.
This doesn't work when trying to load windows GPU driver
for the pass-through GPU device.
For pass-through devices,
set the bar prefetchable property the same as physical bar.
Tracked-On: #4282
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
When update pci bar addr,
DM may change the bar property by func pci_cfgrw.
PCI spec chapter 'Base Addresses' shows
bits 0~3 are readonly of memeory space BAR,
so this change won't happen.
This patch ensures pci bar property unchanged
when update pci bar addr.
Tracked-On: #4282
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
use acrn-dm logger function instread of perror,
this helps the stability testing log capture.
Tracked-On: #4098
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Do reset for passthrough PCI device by default when assigning it to post-launched
VM:
1. modify opt "reset" to "no_reset" -- could enable no_reset for debug only
2. remove "ptdev_no_reset" opt. It could be replaced by setting "no_reset" for
each passthrough device.
Tracked-On: #3465
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This patch refactors the CMD_OPT_LAPIC_PT case branch
to explicity add the dependency of option RTVM at the
same branch, it is decoupled from the next case branch
to comply with strict code standard and improve the
code readability.
Tracked-On: #4283
Signed-off-by: Gary <gordon.king@intel.com>
Now the GVT already tries to reserve the region.
the problem is that the region should be
reflected in PCI BUS0 memlimit32 and updated to DSDT table.
As the GVT PCI bar0/2 is in reserved region
and not updated to memlimit32 in DSDT table,
the problem is triggered.
Tracked-On: projectacrn#4227
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Add the below flags, they are needed in -O2:
-fno-delete-null-pointer-checks:
* tells the compiler NOT to assume that null pointer deference does
not exist.
* Without this flag, below case cannot be detected:
a pointer might point to nullsometime during run-time and if there
is no validation for that pointer, it will cause the program to crash.
Since we don’t receive an error message saying that a pointer is
pointing to null, we will have a hard time trying to find the problem.
-fwrapv:
* tells the compiler that signed overflow always wraps.
* Without this flag, x + 10 > x will always be true for signed x.
With the flag, x + 10 > x is not always be true, as the overflow is
defined for x, and it could wrap.
Tracked-On: #4194
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
Need to enable gvt bar registration, so remove the previous workaround patch.
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The current design has the following problem:
uos kernel may update gvt bars' regions,
but ACRN-DM doesn't know this update.
ACRN-DM only know out-of-date gvt bar regions,
For simplicity, mark these bar regions as OOD bar regions.
uos kernel may allocate OOD bar regions for
other pci devices, which will result in ACRN-DM
bar regions inconsistency with uos kernel.
The new design is the following:
When other pci device update bar regions
(1) ACRN-DM updates gvt bars' regions
provided by a system file.
(2) ACRN-DM updates this pci device bar regions
v5 -> v6:
* add more comments
v4 -> v5:
* remove & for callback func assignment
v3 -> v4:
* compare gpu bar address to avoid unnecessary
* unregistered/registered operation
v2 -> v3:
* call unregister_bar and register_bar when update gvt bars
* update gvt reserved regions when update gvt bars
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
ACRN-DM has reserved gvt bar regions.
This patch ensures other pci devices' bar regions
won't overlap with reserved bar regions.
v6 -> v7:
* rename some struct and func
v5 -> v6:
* remove outdated comment
* add comments for code reading
* code cleaning about gvt bar0 and bar2 size
v4 -> v5:
* rename adjust_bar_region and adjust_bar_region_by_gvt_bars
* change adjust_bar_region_by_gvt_bars interface for code cleaning
v3 -> v4:
* add static struct gvt_region instead of definition or pointer array.
v2 -> v3:
* repalce pci_emul_alloc_bar with gvt_reserve_resource when allocate gvt bars
* use register_bar to detect if gvt bars confilts with pci devices
v1 -> v2:
* don't limit the gvt bar type is MEM32 when deal with pci bar
* add is_two_region_overlap func to detect if two regions overlap
* add region array to store gvt bar0 and bar2 regions
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The current design has the following problem:
gvt uses some pci bar regions,
but ACRN-DM isn't aware of these regions.
So ACRN-DM may allocate these regions for other pci devices,
which will result in other pci devices bar regions
overlap with gvt bar regions.
The new design is the following:
(1) ACRN-DM reads gvt bar regions
which are provided by physical gpu;
(2) ACRN-DM reserves gvt bar regions
v6 -> v7:
* use array to store reserved bar regions
* rename some struct and func
v5 -> v6:
* rename enable_gvt to gvt_enabled
* add a interface to reserve bar regions
* reserve gvt bar regions
Tracked-On: projectacrn#4005
Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
use acrn-dm logger function instread of fprintf,
this helps the stability testing log capture.
Tracked-On: #4098
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Cao Minggui <minggui.cao@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Use acrn-dm logger function instread of printf,
this helps the stability testing log capture.
Tracked-On: #4098
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Cao Minggui <minggui.cao@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
The parameter of intel_pstate should be 'disable' instead of 'disabled'.
This patch fixes it.
Tracked-On: #4094
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
The acrn vhm driver will convert all PCI configure space access to
PCI_CFG type, so the pci_emul_cfgaddr and pci_emul_cfgdata will nerver
be invoked. Remove these useless functions.
Tracked-On: #3999
Signed-off-by: Gao Junhao <junhao.gao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Lock should be held till all the mmap operations are done. This is to
avoid the mmap failure when multiple guests are created concurrently.
For example consider the following case in which vm1 and vm2 are
created by acrnd concurrently:
- vm1 is created with 4G+2M memory.
- 4G+2M memory is reserved in hugetlb now and vm1 continues to
allocate memory for the lowmem without lock held.
- 2G memory is allocated by vm1 for its lowmem, and 2G+2M memory
is available in hugetlb.
- At this time vm2 is created with 1G+2M memory. It finds that enough
memory is reserved (2G+2M), so it does not try to reserve more
memory.
- vm2 allocates some memory for its lowmem/highmem/ovmf.
- vm1 tries to allocate memory for its highmem/ovmf, the allocation
will fail. vm1 creation failed in this case.
Tracked-On: #3947
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
The device model generating ACPI table use the old ASL
standard(version:20190816), then the iasl in clearlinux(version:31360)
is 20191018, it can't disassemble the ACPI table compiled by old
standard.
Tracked-On: #3933
Signed-off-by: Gao Junhao <junhao.gao@intel.com>
Reviewed-by: Fengwei Yin <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
In function crb_reg_write() in tpm_rbc.c
'tpm_vdev->request_mutex' will potentially kept
in locked state after crb_reg_write() returns.
Tracked-On: #3825
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Yadong Qi <yadong.qi@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
Wrong NVMe bdf info of KBLNUC7i7DNH is modified by mistake; so change it back.
Tracked-On: #3827
Reviewed-by: binbin.wu@intel.com
Signed-off-by: fuzhongl <fuzhong.liu@intel.com>
In acrn_load_elf(), file pointer 'fp' is kept in
open state before exiting if 'load_elf32()' is executed,
this patch is to fix this bug.
Tracked-On: #3817
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Tw