Commit Graph

27 Commits

Author SHA1 Message Date
Liang Yi e8a76868c9 hv: modularization: remove global variable efiloader_sig.
Simplify multiboot API by removing the global variable efiloader_sig.
Replaced by constant at the use site.

Tracked-On: #5661
Signed-off-by: Yi Liang <yi.liang@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2021-01-27 15:59:47 +08:00
Liang Yi 67926cee81 hv: modularization: remove include/boot.h.
Remove include/boot.h since it contains only assembly variables that
should only be accessed in arch/x86/init.c.

Tracked-On: #5661
Signed-off-by: Yi Liang <yi.liang@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2021-01-27 15:59:47 +08:00
Zide Chen a776ccca94 hv: don't need to save boot context
- Since de-privilege boot is removed, we no longer need to save boot
  context in boot time.
- cpu_primary_start_64 is not an entry for ACRN hypervisor any more,
  and can be removed.

Tracked-On: #5197
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2020-10-29 10:05:05 +08:00
Victor Sun 0461ac209f HV: set CONFIG_HV_RAM_START as min addr when RELOC enabled
Previously the min load_addr for HV image is hard coded to 0x10000000 when
CONFIG_RELOC is enabled, now use CONFIG_HV_RAM_START as its prefer minimum
address like setting of CONFIG_PHYSICAL_START do in Linux kernel.

With this patch, we can offload the CONFIG_HV_RAM_START algorithm to
acrn-config or manually set it in scenario XML on some special boards.

Tracked-On: #5275

Signed-off-by: Victor Sun <victor.sun@intel.com>
2020-09-07 15:03:53 +08:00
Li Fei1 6e57553015 Revert "hv: Let trampoline execution use 1GB pages"
This patch tries to release hardware platform 1GB large page support constrain
on CPU side.

There're some silicon bug on lakefield, TNT and EHL platforms which cause CPU
couldn't support 1GB large page. As a result, the pre-assumption The platform
which ACRN supports must support 1GB large page on both CPU side and VTD side
is not true any more.

This reverts commit f01aad7e to let trampoline execution use 2MB pages.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-06-15 15:16:34 +08:00
Minggui Cao 691a0e2e56 HV: add a specific stack space used in CPU booting
The original stack used in CPU booting is: ld_bss_end + 4KB;
which could be out of the RAM size limit defined in link_ram file.

So add a specific stack space in link_ram file, and used in
CPU booting.

Tracked-On: #4738
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-29 13:56:40 +08:00
Victor Sun 52f26cba8a hv: a few fixes for multiboot2 boot
- need to specify the load_addr in the multiboot2 address tag. GRUB needs
  it to correctly calculate the ACRN binary's load size if load_end_addr is
  a non-zero value.

- multiboot2 can be enabled if hypervisor relocation is disabled.

- print the name of the boot loader. This might be helpful if the boot
  loader, e.g. GRUB, inludes its version in the name string.

Tracked-On: #4441
Signed-off-by: Victor Sun <victor.sun@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2020-03-24 08:44:20 +08:00
Zide Chen 67cb1029d9 hv: update the hypervisor 64-bit entry address for efi-stub
- remove .data and .text directives. We want to place all the boot data and
  text in the .entry section since the boot code is different from others
  in terms of relocation fixup. With this change, the page tables are in
  entry section now and it's aligned at 4KB.

- regardless CONFIG_MULTIBOOT2 is set or not, the 64-bit entry offset is
  fixed at 0x1200:

  0x00 -- 0x10: Multiboot1 header
  0x10 -- 0x88: Multiboot2 header if CONFIG_MULTIBOOT2 is set
  0x1000: start of entry section: cpu_primary_start_32
  0x1200: cpu_primary_start_64 (thanks to the '.org 0x200' directive)
          GDT tables
	  initial page tables
	  etc.

Tracked-On: #4441
Reviewed-by: Fengwei Yin <fengwei.yin@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
2020-03-06 08:27:46 +08:00
Zide Chen 49ffe168af hv: fixup relocation delta for symbols belong to entry section
This is to enable relocation for code32.

- RIP relative addressing is available in x86-64 only so we manually add
  relocation delta to the target symbols to fixup code32.

- both code32 and code64 need to load GDT hence both need to fixup GDT
  pointer. This patch declares separate GDT pointer cpu_primary64_gdt_ptr
  for code64 to avoid double fixup.

- manually fixup cpu_primary64_gdt_ptr in code64, but not rely on relocate()
  to do that. Otherwise it's very confusing that symbols from same file could
  be fixed up externally by relocate() or self-relocated.

- to make it clear, define a new symbol ld_entry_end representing the end of
  the boot code that needs manually fixup, and use this symbol in relocate()
  to filter out all symbols belong to the entry sections.

Tracked-On: #4441
Reviewed-by: Fengwei Yin <fengwei.yin@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
2020-03-06 08:27:46 +08:00
Chen, Zide 2aa8c9e5d4 hv: add multiboot2 tags to load relocatable raw binary
GRUB multiboot2 doesn't support relocation for ELF, which means it can't
load acrn.32.out to other address other than the one specified in ELF
header. Thus we need to use the raw binary file acrn.bin, and add
address/entry address/relocatable tags to instruct multiboot2 loader
how to load the raw binary.

Tracked-On: #4441
Reviewed-by: Fengwei Yin <fengwei.yin@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
2020-03-06 08:27:46 +08:00
Chen, Zide 97fc0efe20 hv: remove unused cpu_primary_save_32()
In direct boot mode, boot_context[] which is saved from cpu_primary_save_32()
is no longer used since commit 6beb34c3cb ("vm_load: update init gdt
preparation"). Thus, the call to it and the function itself can be removed.

Tracked-On: #4441
Reviewed-by: Fengwei Yin <fengwei.yin@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
2020-03-06 08:27:46 +08:00
Victor Sun da3d181f62 HV: init efi info with multiboot2
Initialize efi info of acrn mbi when boot from multiboot2 protocol, with
this patch hypervisor could get host efi info and pass it to Linux zeropage,
then make guest Linux possible to boot with efi environment;

Tracked-On: #4419

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-26 09:24:16 +08:00
Victor Sun 69da0243f5 HV: init module and rsdp info with multiboot2
Initialize module info and ACPI rsdp info of acrn mbi when boot from
multiboot2 protocol, with this patch SOS VM could be loaded sucessfully
with correct ACPI RSDP;

Tracked-On: #4419

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-26 09:24:16 +08:00
Victor Sun d008b72fdd HV: add multiboot2 header info
Add multiboot2 header info in HV image so that bootloader could
recognize it.

Tracked-On: #4419

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-26 09:24:16 +08:00
Victor Sun 520a0222d3 HV: re-arch boot component header
The patch re-arch boot component header files by:

- moving multiboot.h from include/arch/x86/ to boot/include/ and keep
  this header for multiboot1 protocol data struct only;

- moving multiboot related MACROs in cpu_primary.S to multiboot.h;

- creating an independent boot.h to store acrn specific boot information
  for other files' reference;

Tracked-On: #4419

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-26 09:24:16 +08:00
Sainath Grandhi f01aad7e77 hv: Let trampoline execution use 1GB pages
ACRN currently uses 2MB large pages in the page tables setup
for trampoline code and data. This patch lets ACRN use 1GB large
pages instead.
When it comes to fixing symbols in trampoline code, fixing pointers
in PDPT is no more needed as PDPT PTEs contain Physical Address.

Tracked-On: #3899
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-10-28 13:44:32 +08:00
Mingqiang Chi da9ed0eda9 hv:remove some unnecessary includes
remove some unnecessary includes

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2019-05-07 09:10:13 +08:00
Kaige Fu a85d11ca7a HV: Add prefix 'p' before 'cpu' to physical cpu related functions
This patch adds prefix 'p' before 'cpu' to physical cpu related functions.
And there is no code logic change.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-24 10:50:28 +08:00
Jason Chen CJ 689c1c28c5 function name change in init.c
- bsp_boot_init to init_primary_cpu
- bsp_boot_post to init_primary_cpu_post

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-12-19 09:07:14 +08:00
Yin Fengwei 69dc939243 hv: drop the temperory stack for AP startup
By switching AP wakeup from broadcast to one by one, we could
set correct stack for each AP and drop the temp stack used during
AP boot.

Tracked-On: #2034
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-17 19:16:43 +08:00
Yonghua Huang 4d13ad9d08 hv: enable NX in hypervisor
- enable NX feature in hypervisor:
  1. Set 'XD' bit for all pages, including pages for guests
     when initialize MMU tables in hypervisor.
  2. remove 'XD' bit for pages that contain hypervisor instructions.
  3. enable MSR EFER.NXE,which will enable page access restriction by
     preventing instruction fetches form pages with XD bit set.

- remove "-Wl -z noexecstack" GCC flag option in hypervisor
  Makefile as it would not affect stack attribute in hyervisor,
  which setup stack itself, instead of by loader.

Tracked-On: #1122
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-12 12:53:18 +08:00
Jason Chen CJ c2be20d2a0 move idt.S and idt.h out of boot component
based on previous patch, we can move idt.S and idt.h out of boot component

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-12 09:07:43 +08:00
Jason Chen CJ 27938c3300 move idt fixup out of cpu_primary.S
we will not enable interrupt until interrupt_init, so we can defer idt
fixup and lidt to interrupt_init.

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-12 09:07:43 +08:00
Jason Chen CJ 6b42b347d5 init fs and gs with 0x10
we are not using ldt, so just init fs & gs with 0x10 which lead to
data segement descriptor in gdt.

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-12 09:07:43 +08:00
Shiqing Gao 2f15d3569c hv: replace CPU_PAGE_SIZE with PAGE_SIZE
replace CPU_PAGE_SIZE with PAGE_SIZE
These two MACROs are duplicated and PAGE_SIZE is a more reasonable name.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-03 15:14:57 +08:00
Jason Chen CJ aa9af27338 modularization: boot component
Boot component prepares the very basic platform boot env. It finally call
into platform initilization entries:

- bsp_boot_init & cpu_secondary_init for start up
- or restore_s3_context for wakeup

this patch is the final one, it did some code clean up and move some definition
from vm0_boot.h to boot_context.h.

after this patch, the boot component include files:
arch/x86/boot/cpu_primary.S
arch/x86/boot/trampoline.S
arch/x86/boot/cpu_save_boot_ctx.S
arch/x86/boot/idt.S
boot/reloc.c
boot/include/reloc.h
include/arch/x86/boot/idt.h
include/arch/x86/boot/boot_context.h

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-12-03 09:09:44 +08:00
Jason Chen CJ 0bc85d2ebc modularization: boot component - move files
Boot component prepares the very basic platform boot env. It finally call
into platform initilization entries:

- bsp_boot_init & cpu_secondary_init for start up
- or restore_s3_context for wakeup

This patch just move files into reorg dir.

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-11-29 15:44:56 +08:00