Commit Graph

3370 Commits

Author SHA1 Message Date
Conghui 51e6dc5864 hv: sched: fix bug when reboot vm
BVT schedule rule:
When a new thread is wakeup and added to runqueue, it will get the
smallest avt (svt) from runqueue to initiate its avt. If the svt is
smaller than it's avt, it will keep the original avt. With the svt, it
can prevent a thread from claiming an excessive share of CPU after
sleepting for a long time.

For the reboot issue, when the VM is reboot, it means a new vcpu thread
is wakeup, but at this time, the Service VM's vcpu thread is blocked,
and removed from the runqueue, and the runqueue is empty, so the svt is
0. The new vcpu thread will get avt=0. avt=0 means very high priority,
and can run for a very long time until it catch up with other thread's
avt in runqueue.
At this time, when Service VM's vcpu thread wakeup, it will check the
svt, but the svt is very small, so will not update it's avt according to
the rule, thus has a very low priority and cannot be scheduled.

To fix it, update svt in pick_next handler to make sure svt is align
with the avt of the first obj in runqueue.

Tracked-On: #7944
Signed-off-by: Conghui <conghui.chen@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
2022-08-05 02:39:54 +08:00
Yonghua Huang 95a938e50a hv: validate inputs in vpci_mmio_cfg_access
This function is registered as PCI MMIO configuration
  access handler, which processes PCI configuration access
  request from ACRN guest hence the inputs shall be validated
  to avoid potential hypervisor crash when handling inputs
  from malicious guests.

Tracked-On: #7902
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2022-07-29 10:30:08 +08:00
Minggui Cao 83164d6030 hv: shell: improve console to modify input easier
1. make memcpy_erms as a public API; add a new one
  memcpy_erms_backwards, which supports to copy data from tail to head.

  2. improve to use right/left/home/end key to move cursor, and support
delete/backspace key to modify current input command.

Tracked-On: #7931
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2022-07-28 23:31:43 +08:00
Minggui Cao d5b2c82156 hv: shell: improve console to buffer history cmds
1. buffer history commands.
  2. support up/down key to select history buffered commands

Tracked-On: #7931
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2022-07-28 23:31:43 +08:00
Jian Jun Chen 22a302599a hv: tlfs: fix the incorrect vLAPIC freq MSR
When LAPIC timer is working in oneshot or periodic mode, OS uses
initial counter register/current counter register to program
a timer. Both initial counter and current counter depend on the
LAPIC frequency. ACRN emulated vLAPIC timer based on the TSC.
vLAPIC freq is the same as TSC freq.

Tracked-On: #7876
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2022-07-26 05:53:19 +08:00
Yifan Liu 4f4da08490 hv: cve hotfix: Disable RRSBA on platform using retpoline
For platform that supports RRSBA (Restricted Return Stack Buffer
Alternate), using retpoline may not be sufficient to guard against branch
history injection or intra-mode branch target injection. RRSBA must
be disabled to prevent CPUs from using alternate predictors for RETs.

Quoting Intel CVE-2022-0001/CVE-2022-0002:

Where software is using retpoline as a mitigation for BHI or intra-mode BTI,
and the processor both enumerates RRSBA and enumerates RRSBA_DIS controls,
it should disable this behavior.
...
Software using retpoline as a mitigation for BHI or intra-mode BTI should use
these new indirect predictor controls to disable alternate predictors for RETs.

See: https://www.intel.com/content/www/us/en/developer/articles/technical/
 software-security-guidance/technical-documentation/branch-history-injection.html

Tracked-On: #7907
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
2022-07-22 09:38:41 +08:00
Jian Jun Chen c88860250e hv: tlfs: add tlfs TSC freq MSR support for WaaG
TLFS defined 2 vMSRs which can be used by Windows guest to get the
TSC/APIC frequencies from hypervisor. This patch adds the support
of HV_X64_MSR_TSC_FREQUENCY/HV_X64_MSR_APIC_FREQUENCY vMSRS whose
availability is exposed by CPUID.0x40000003:EAX[bit11] and EDX[bit8].

v1->v2:
- revise commit message to highlight that the changes are for WaaG

Tracked-On: #7876
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
2022-07-18 16:15:29 +08:00
Jian Jun Chen 97a2919138 hv: tsc: calibrate TSC by HPET
On some platforms CPUID.0x15:ECX is zero and CPUID.0x16 can
only return the TSC frequency in MHZ which is not accurate.
For example the TSC frequency obtained by CPUID.0x16 is 2300
MHZ and the TSC frequency calibrated by HPET is 2303.998 MHZ
which is much closer to the actual TSC frequency 2304.000 MHZ.
This patch adds the support of using HPET to calibrate TSC
when HPET is available and CPUID.0x15:ECX is zero.

v3->v4:
  - move calc_tsc_by_hpet into hpet_calibrate_tsc

v2->v3:
  - remove the NULL check in hpet_init
  - remove ""& 0xFFFFFFFFU" in tsc_read_hpet
  - add comment for the counter wrap in the low 32 bits in
    calc_tsc_by_hpet
  - use a dedicated function for hpet_calibrate_tsc

v1->v2:
  - change native_calibrate_tsc_cpuid_0x15/0x16 to
    native_calculate_tsc_cpuid_0x15/0x16
  - move hpet_init to BSP init
  - encapsulate both HPET and PIT calibration to one function
  - revise the commit message with an example"

Tracked-On: #7876
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
2022-07-17 16:48:47 +08:00
Ziheng Li eb8bcb06b3 Update copyright year range in code headers
Modified the copyright year range in code, and corrected "int32_tel"
into "Intel" in two "hypervisor/include/debug/profiling.h" and
"hypervisor/include/debug/profiling_internal.h".

Tracked-On: #7559
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
2022-07-15 11:48:35 +08:00
Yifan Liu 05460f151a hv: Serialize WBINVD using wbinvd_lock
As mentioned in previous patch, wbinvd utilizes the vcpu_make_request
and signal_event call pair to stall other vcpus. Due to the fact that
these two calls are not thread-safe, we need to avoid concurrent call to
this API pair.

This patch adds wbinvd lock to serialize wbinvd emulation.

Tracked-On: #7887
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2022-07-14 09:05:37 +08:00
Yifan Liu 745e70fb06 hv: Change sched_event back to boolean-based implementation
Commit d575edf79a changes the internal
implementation of wait_event and signal_event to use a counter instead
of a boolean value.

The background was:
ACRN utilizes vcpu_make_request and signal_event pair to shoot down
other vcpus and let them wait for signals. vcpu_make_request eventually
leads to target vcpu calling wait_event.

However vcpu_make_request/signal_event pair was not thread-safe,
and concurrent calls of this pair of API could lead to problems.
One such example is the concurrent wbinvd emulation, where vcpus may
concurrently issue vcpu_make_request/signal_event to synchronize wbinvd
emulation.

d575edf commit uses a counter in internal implementation of
wait_event/signal_event to avoid data races.

However by using a counter, the wait/signal pair now carries semantics of
semaphores instead of events. Semaphores require caller to carefully
plan their calls instead of multiply signaling any number of times to the same
event, which deviates from the original "event" semantics.

This patch changes the API implementation back to boolean-based, and
re-resolve the issue of concurrent wbinvd in next patch.

This also partially reverts commit 10963b04d1,
which was introduced because of the d575edf.

Tracked-On: #7887
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2022-07-14 09:05:37 +08:00
Shiqing Gao 3eb1237db3 config_tools: verify "iasl" version against IASL_MIN_VER
To avoid hardcoding the minimum "iasl" version in multiple places, IASL_MIN_VER
is defined in the top-level Makefile and is passed to config_tools.

This patch verifies "iasl" version against IASL_MIN_VER directly in
config_tools.

Tracked-On: #7880

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
2022-07-13 14:01:01 +08:00
Shiqing Gao 3f0fae81b2 config_tools: use ASL_COMPILER as the path to the "iasl" compiler
At build time (on the *dev* machine), config_tools depends on "iasl" to
generate the binary of ACPI tables for pre-launched VMs.

This patch does:
- pass ASL_COMPILER to config_tools
  By default, ASL_COMPILER is initialized by "which iasl" at build time.
  User could override it by specifying ASL_COMPILER as the build option,
  like below:
    make BOARD=xxxx SCENARIO=yyyy ASL_COMPILER=/usr/local/bin/iasl

- use ASL_COMPILER as the path to the "iasl" compiler in config_tools

v1 -> v2:
 - add a check to make sure ASL_COMPILER is initialized to a value

Tracked-On: #7880

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
2022-07-13 14:01:01 +08:00
Qiang Zhang 95c4d18423 hv: compile out unused function if CONFIG_MULTIBOOT2 is disabled
When CONFIG_MULTIBOOT2 is disabled, 'create_service_vm_efi_mmap_desc' is
unused and build fails because [-Werror=unused-function] is set.

boot/guest/bzimage_loader.c:188:17: error: 'create_service_vm_efi_mmap_desc' defined but not used [-Werror=unused-function]
  188 | static uint16_t create_service_vm_efi_mmap_desc(struct acrn_vm *vm, struct efi_memory_desc *efi_mmap_desc)
      |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors

Tracked-On: #7634
Signed-off-by: Qiang Zhang <qiang4.zhang@linux.intel.com>
2022-07-07 11:25:31 +08:00
Geoffroy Van Cutsem bb30301e23 Update TSC members and maintainers
Updates to the TSC members and maintainer list
* Update the Technical Steering Committee (TSC) members following the election
of Junjie Mao as the new chair
* Update Thomas Gleixner's email address since he joined Intel Corporation
* Delete the MAINTAINERS files in the 'hypervisor' and 'devicemodel' folders
  as they are obsolete and unused.

Tracked-On: #7706
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
2022-06-08 14:14:27 +08:00
Yonghua Huang b304df0f6b hv: debug: fix type size mismatch in get_entry_info
In 'get_ptdev_info()', variables 'bdf' and 'vbdf' are
 16bits in size but their base addresses are converted
 to 32bit pointers when calling 'get_entry_info()'.

 This mismatch causes insufficient space when storing
 to memory pointer by 'bdf' or 'vbdf' in 'get_entry_info()',
 where those pointers are regarded as 32bits width memory.

 This patch refines definition of 'get_entry_info()'.

Tracked-On: #7547
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2022-05-24 10:00:43 +08:00
Fei Li df3390f401 hv: vtd: reset the one-shot bits for GCMD_REG
If multiple control fields in GCMD_REG register need to be modified, software
must serialize the modifications through multiple writes to this register.

So one-shot bits (bits 30-29, 27 and 24) in gcmd should not been set.
Otherwise, other control field may be written to GCMD_REG at the same time
with one-shot bit (Clearing one-shot bit has no effect, software sets this field
would set/update this control field used by hardware).

Tracked-On: #7381
Signed-off-by: Fei Li <fei1.li@intel.com>
2022-05-20 09:30:25 +08:00
Chenli Wei 5f0588b5f8 hv: move the define of MAX_IR_ENTRIES to offline tool
There is an issue of calculate 2^n roundup of CONFIG_MAX_PT_IRQ_ENTRIES,
and the code style is very ugly when we use macro to fix it.

So this patch move MAX_IR_ENTRIES to offline tool which could do align
check and calculate it automatically.

Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
2022-05-20 09:08:47 +08:00
Yuanyuan Zhao 3062aa409f hv: fix build warning with gcc-11.2
dm/vrtc.c:565:33: error: 'current' may be used uninitialized in this
function.[-Werror=maybe-uninitialized]

Move the local variable definition into one code block to avoid warning.

Tracked-on: #7511
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
2022-05-19 14:44:35 +08:00
Chenli Wei c96fb1cb0a hv: move the MAX_VUART_NUM_PER_VM to offline tool
Current code limit the MAX vUART number to 8 which is not enough for
Service VM which should config S5 UART for each user VM.

We could count how many vUARTs we need by offline tool, so remove the
define of MAX_VUART_NUM_PER_VM to offline tool is a simple and accurate
way to allocate vUARTs.

Tracked-On: #8782
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
2022-05-13 13:50:07 +08:00
Fei Li d233a0d30f hv: crypto: fix a minor build Werror
The comparison "ctx->md_info == NULL" (if ctx is not NULL) will always evaluate
as 'false' for the address of 'hmac_ctx' will never be NULL.
This patch remove this unnecessary check.

Tracked-On: #7453
Signed-off-by: Fei Li <fei1.li@intel.com>
2022-05-13 10:47:51 +08:00
Yuanyuan Zhao a65a347f34 hv: vRTC monotonic growth
For physical RTC is monotonic growth, ensure vRTC monotonicity.
Periodical calibration and physical RTC modification may have
impact. Check it before reading

Tracked-On: #7440
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-05-12 13:20:21 +08:00
Yuanyuan Zhao 145a56d448 hv: calibrate vrtc when modify physical time
For Service VM modify physical rtc time and vrtc will calibrate
time by read physical rtc. So when Service VM modify physical
time, calibrate all vrtc.

Tracked-On: #7440
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-05-12 13:20:21 +08:00
Yuanyuan Zhao 4bad719fd3 hv: vrtc calibrate function
For TSC's precision (20~100ppm) is lower than physical RTC (less than 20ppm),
vRTC need to be calibrated by physical RTC. A timer tiggers calibration for
vRTC every 3 hours. This can improve efficiency because physical RTC can be
read once and calibrate all vRTC.

Tracked-On: #7440
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-05-12 13:20:21 +08:00
Yuanyuan Zhao 08e8161f51 hv: add time modification of vrtc
VRTC for hv used to ignore writes to vRTC register.

This patch add time modification to vRTC.
Add base RTC time and TSC offset to get the current time. Convert
current time to vRTC register values (`struct rtcdev`). Then
modify a register, and calculate a new time. Get RTC offset by
substrcting new time from current time.
Thereafter, add RTC offset also when get current time. Then user
can get the modified time.

Tracked-On: #7440
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-05-12 13:20:21 +08:00
Yuanyuan Zhao bca21648a3 hv: add Service VM write physical RTC register
Service VM write physical RTC register.
Both RTC time modify and Configuration register is available.

Tracked-On: #7440
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-05-12 13:20:21 +08:00
Yuanyuan Zhao dfdf79ffa9 hv: add vRTC reg_b and reg_c support
During setting RTC time, driver will halt RTC update. So support
bit 7 of reg_b. When it set to 0, time will be updated. And
when it's set to 1, rtc will keep the second it was set.

In the process of getting RTC time, driver sets alarm interrupt,
waits 1s, and get alarm interrupt flag. So support alarm interrupt
flag update. If alarm interrupt is enabled (bit 5, reg_b set to 1),
interrupt flag register will be set (bit 7 & bit 5 of reg_c) at
appropriate time.

Tracked-On: #7440
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-05-12 13:20:21 +08:00
Yuanyuan Zhao 6ade2b6b0c hv: support 12 hour mode
Add support for hour format.
Bit 1 of register B indicates the hour byte format. When it's 0,
twelve-hour mode is selected. Then the seventh bit of hour register
presents AM as 0 and PM as 1.

Tracked-On: #7440
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-05-12 13:20:21 +08:00
Yuanyuan Zhao ac89244cf5 hv: support vrtc BCD data mode
Add judging of the vRTC data mode. If BCD data mode is inuse,
make conversion of data.

Tracked-On: #7440
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-05-12 13:20:21 +08:00
Yuanyuan Zhao 23177d0a1d hv: add `rtcdev` emulate vrtc
Current code would read physical RTC register and return it directly to guest.

This patch would read a base physical RTC time and a base physical TSC time
at initialize stage. Then when guest tries to read vRTC time, ACRN HV would
read the real TSC time and use the TSC offset to calculate the real RTC time.

This patch only support BIN data mode and 24 hour mode.
BCD data mode and 12 hour mode will add in other patch.
The accuracy of clock provided by this patch is limited by TSC, and will
be improved in a following patch also.

Tracked-On: #7440
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-05-12 13:20:21 +08:00
Yonghua Huang 961b5d16f4 hv: update SSRAM regions EPT memory type to WB
when SSRAM regions are assigned to service VM
  to support virtulization of SSRAM for post-launched
  RTVMs, service VM need to access all SSRAM regions
  for management, typically, service VM does data
  cleanup in SSRAM region when it is reclaimed from
  a shutdown RTVM.

  This patch update memory type from UC(by default)
  to WB, else SSARM region will be evicted when access
  from guest happens.

Tracked-On: #7425
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2022-05-10 15:45:52 +08:00
Helmut Buchsbaum aa8d636507 hv: Fixup serial.conf permissions
Tracked-On: #6688
Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@opensource.tttech-industrial.com>
2022-05-10 09:20:14 +08:00
Zhou, Wu 3ba5b1522f hv: fix post RTVM booting failure with SSRAM
When booting prelaunch RTVM with SSRAM enabled, we need to delete the
SSRAM region that is used by prelaunch RTVM from Service VM EPT mapping.
If it is not used, or it is not fully used, the SSRAM or the rest SSRAM
should be in Service VM map.

But current code has a issue that it always deletes all SSRAM region
from Service VM EPT, even when no SSRAM is enabled for prelaunch RTVM.

This could cause the post RTVM with SSRAM boot failure, as DM checks and
removes SSRAM region from Service VM EPT during post RTVM setup.

Changing get_software_sram_size() to PRE_RTVM_SW_SRAM_MAX_SIZE could
solve the issue, as PRE_RTVM_SW_SRAM_MAX_SIZE is the SSRAM size that
prelaunch RTVM actually uses.

Tracked-On: #7401

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
2022-05-06 14:41:58 +08:00
Jiang, Yanting 599894e571 Fix: write xmm registers correctly
The movdqu instruction moves unaligned double quadword (128 bit)
contained in XMM registers.

This patch uses pointers as input parameters of the function
write_xmm_0_2() to get 128-bit value from 64-bit array for each XMM
register.

Tracked-On: #7380
Reviewed-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Jiang, Yanting <yanting.jiang@intel.com>
2022-05-06 10:29:33 +08:00
Fei Li 5130dfe08b hv: vSRIOV: add VF BARs mapping for PF
When enabling SRIOV capability for a PF in Service VM, ACRN Hypervisor
should add VF BARs mapping for PF since PF's firmware would access these
BARs to do initialization for VFs when it's first created.

Tracked-On: #4433
Signed-off-by: Fei Li <fei1.li@intel.com>
2022-04-26 15:07:25 +08:00
Fei Li 13e99bc0b9 hv: vPCI: passthrough MSI-X Control Register to guest.
In spite of Table Size in MSI-X Message Control Register [Bits 10:0] masks as
RO (Register bits are read-only and cannot be altered by software), In Spec
PCIe 6.0, Chap 6.1.4.2 MSI-X Configuration "Depending upon system software
policy, system software, device driver software, or each at different times or
environments may configure a Function’s MSI-X Capability and table structures
with suitable vectors."

This patch just pass through MSI-X Control Register field to guest.

Tracked-On: #7275
Signed-off-by: Fei Li <fei1.li@intel.com>
2022-04-26 15:07:25 +08:00
Tw e2f7b1fc51 hv: remove obsolete declarations related to RDT
Since CAT support for hybrid platform is landed, let's remove some old declarations
which are no longer used.

Tracked-On: #6690
Signed-off-by: Tw <wei.tan@intel.com>
2022-04-26 14:27:01 +08:00
Conghui a2e2640507 config-tools: ignore the scenario and board field
Ignore the "scenario" and "board" field in <scenario>.xml:
    <acrn-config board="whl-ipc-i5" scenario="shared">

Tracked-On: #7345
Signed-off-by: Conghui <conghui.chen@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-04-24 13:53:32 +08:00
Conghui 593414e9c2 config-tools: support absolute path
1. Support absolute path for scenario file.
2. Use the scenario xml file name as scenario name, but if it is
'scenario.xml', use the upper level directory name.
e.g.
	SCENARIO=<pathxxx>/shared/scenario.xml
Then scenario name would be 'shared'.

3. Change 'realpath' to 'abspath' as we should keep the original path
for scenario file even it is a link file. This will make sure the
scenario name is always consistent with file set in 'SCENARIO='.

Tracked-On: #7345
Signed-off-by: Conghui <conghui.chen@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-04-24 13:53:32 +08:00
Chenli Wei ed1c638c87 hv: refine for HPAn setting
The current code only supports 2 HPA regions per VM.

This patch extended ACRN to support 2+ HPA regions per VM, to use host
memory better if it is scatted among multiple regions.

This patch uses an array to describe the hpa region for the VM, and
change the logic of ve820 to support multiple regions.

This patch dependent on the config tool and GPA SSRAM change

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
2022-04-22 14:46:05 +08:00
Tw e246ada6b0 hv: fix core type error when launch RTVM use atom core
When CPUID executes with EAX set to 1AH, the processor returns information about hybrid capabilities.
This information is percpu related, and should be obtained directly from the physical cpu.

Tracked-On: #6899
Signed-off-by: Tw <wei.tan@intel.com>
2022-04-21 09:21:16 +08:00
Yonghua Huang 80292a482d hv: remove pgentry_present field in struct pgtable
Page table entry present check is page table type
  specific and static, e.g. just need to check bit0
  of page entry for entries of MMU page table and
  bit2~bit0 for EPT page table case. hence no need to
  check it by callback function every time.

  This patch remove 'pgentry_present' callback field and
  add a new bitmask field for this page entry present check.
  It can get better performance especially when this
  check is executed frequently.

Tracked-On: #7327
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
2022-04-20 17:38:02 +08:00
Tw deb35a0de9 hv: fix cpuid 0x2 mismatch when launch RTVM use atom core
When CPUID executes with EAX set to 02H, the processor returns information about cache and TLB information.
This information is percpu related, and should be obtained directly from the physical cpu.

BTW, this patch is backported from v2.7 branch.

Tracked-On: #6931
Signed-off-by: Tw <wei.tan@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
2022-04-20 16:13:10 +08:00
Zhou, Wu 6458a3f474 hv: remove an unnecessary code line
This patch is to eliminate a code scan warning.

p_elf_header32 was given a value when it was declared, but later it was
given the same value again. Just remove the later one.

Tracked-On: #7318

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
2022-04-20 14:15:25 +08:00
Fei Li 6b32b28e72 hv: ptdev: address vector scalability problem by interrupt posting
Now interrupt vector in ACRN hypervisor is maintained as global variable, not
per-CPU variable. If there're more PCI devices, the physical interrupt vectors
are not enough most likely.

This patch would not allocate physical interrupt vector for MSI/MSI-X vectors
if interrupt posting could been used to inject the MSI/MSI-X interrupt to
a VM directly.

Tracked-On: #7275
Signed-off-by: Fei Li <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2022-04-19 14:54:04 +08:00
Zhou, Wu 32cb5954f2 hv: refine the hard-coded GPA SSRAM area size
Using the SSRAM area size extracted by config_tools, the patch changes
the hard-coded GPA SSRAM area size to its actual size, so that
pre-launched VMs can support large(>8MB) SSRAM area.

When booting service VM, the SSRAM area has to be removed from Service
VM's mem space, because they are passed-through to the pre-rt VM. The
code was bugged since it was using the SSRAM area's GPA in the pre-rt
VM. Changed it to GPA in Service VM.

Tracked-On: #7212

Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
2022-04-18 16:47:23 +08:00
Tw 3c384a489c hv: support CAT on hybrid platform
On hybrid platform(e.g. ADL), there may be multiple instances of same level caches for different type of processors,
The current design only supports one global `rdt_info` for each RDT resource type.
In order to support hybrid platform, this patch introduce `rdt_ins` to represents the "instance".
Also, the number of `rdt_info` is dynamically generated by config-tool to match with physical board.

Tracked-On: projectacrn#6690
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2022-04-18 15:33:11 +08:00
Tw 19da21c898 hv: remove RDT information detection
As RDT related information will be offered by config-tool dynamically,
and HV is just a consumer of that. So there's no need to do this detection
at startup anymore.

Tracked-On: projectacrn#6690
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2022-04-18 15:33:11 +08:00
Geoffroy Van Cutsem 8b16be9185 Remove "All rights reserved" string headers
Many of the license and Intel copyright headers include the "All rights
reserved" string. It is not relevant in the context of the BSD-3-Clause
license that the code is released under. This patch removes those strings
throughout the code (hypervisor, devicemodel and misc).

Tracked-On: #7254
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
2022-04-06 13:21:02 +08:00
Kunhui-Li 74dc103d9e config_tools: remove board and scenario attributes
remove board and scenario attributes dependency for new configuration.

To do:
will remove board and scenario attributes in all scenario XML files
and update the upgrader.py after the new configuration works.

Tracked-On: #6690
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-03-31 19:32:52 +08:00