Commit Graph

1340 Commits

Author SHA1 Message Date
Jason Chen CJ 63ef1236de move global x2apic_enabled into arch dir
the x2apic_enabled should be x86 specific field.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-08-07 09:55:13 +08:00
Jason Chen CJ 72f9c9a26e pm: use cpu_context for s3 save/restore
use structure cpu_context and update offsets in wakeup.S

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-07 09:55:13 +08:00
Jason Chen CJ 8a95b2abdc vcpu: add ext context support for world switch
move most of fields from run_context into ext_context for world switch.
these fields do not need doing runtime save/restore during vm exit/entry.

v3:
- update cr0/cr4 registers switch method

v2:
- use struct name ext_context instead of saved_context
- updated according to previous v2 patch

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-07 09:55:13 +08:00
Jason Chen CJ 3d5d6c96ec vcpu: add get/set register APIs
there will be 3 types of vcpu runtime contexts:
- runtime contexts always saved/restored during VM exit/entry, which
  include general registers rax/rcx/rdx/rbx/rbp/rsi/rdi/r8~r15, cr2 and
  msr for spectre control (ia32_spec_ctrl)
- runtime contexts on-demand cached/updated during VM exit/entry, which
  include frequently used registers rsp, rip, efer, rflags, cr0 and cr4
- runtime contexts always read/write from/to VMCS, which include left
  registers not in above

this patch add get/set register APIs for vcpu runtime contexts, and unified
the save/restore method for them according to above description.

v3:
- update vcpu_get/set_cr0/4 as unified interface to get/set guest cr0/cr4,
  use on-demand cache for reading, but always write to VMCS for writing.

v2:
- use reg_cached/reg_updated for on-demand runtime contexts
- always read/write cr3 from/to VMCS

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-07 09:55:13 +08:00
Xiangyang Wu 5aa1ad3bfc HV:treewide:fix value outside range of underlying type
There are potential value outside range of underlying type
in some assignment expressions. This violates Rule 10.3 or
Rule 10.4 of MISRA C:2012.
BTW, all operations shall be conducted in exactly the same
arithmetic (underlying) type, otherwise, there is a
value outside range violation.

Update related assignment expressions.

V1-->V2:
	* Fix potential overflow in "pit_calibrate_tsc";
	* Move PTDEV_INVALID_PIN definition before
	  get_entry_info since this MACRO is only used by
	  debug function.

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-06 16:07:41 +08:00
Yan, Like c663267b03 hv: timer: request timer irq once only
Since global vector table is being used on all pcpus, it's not necessary to request timer irq
at each cpu init. With this change, per_cpu timer nodes are removed, and only BSP registers
and unregisters timer irq.

Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-06 16:06:22 +08:00
Shiqing Gao b4a2ff5022 hv: treewide: fix 'Prototype and definition name mismatch'
Fix the parameter name mismatch between API declaration and definition.

v2 -> v3:
 * Fix two more violations which are missed in previous report.
   shell_puts and console_write

v1 -> v2:
 * Replace 'ret_desc' with 'desc'

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-06 16:04:40 +08:00
Yu Wang f42878ee3a hv: apicv: improve the default apicv reset flow
Two improvements:

Firstly, disable EOI VMEXIT for all vectors by default. Only the level
sensitive irq need to set it due to need emulate send EOI to vioapic to
clear Remote IRR bit.

Secondly, to clear RVI(Requesting virtual interrupt) and SVI(Servicing
virtual interrupt) bits.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang 6e86d4841d hv: vioapic: set remote IRR to zero once trigger mode switch to edge
In some special scenarios, the LAPIC somehow hasn't send EOI to IOAPIC
which cause the Remote IRR bit can't be clear. To clear it, some OSes
will use EOI Register to clear it for 0x20 version IOAPIC, otherwise
use switch Trigger Mode to Edge Sensitive to clear it.

This patch emulate this IOAPIC behavior to satisfy this requirement.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang 1e1886794e hv: vioapic: remove EOI register support
The IOAPIC specification defined EOI register for 0x20 version. The
original vioapic code implemented this register but the version was
still export as 0x11.

Tried to set 0x20, the Linux kernel has't access this EOI register,
still rely on lapic to send eoi.

From Linux ioapic driver comments, it says that only send EOI via EOI
register when met IOAPIC hardware bug.

This patch removes all 0x20 IOAPIC code to reduce the code size.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang f96f048f71 hv: vioapic: change the variable type of pin to uint32_t
To make vioapic simpler, avoid lots of code to convert variable type
between uint8_t and uint32_t.

This patch changes all variable type of pin related variables to
uint32_t instead of original uint_8.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang b13882f8bd hv: vioapic: improve the vioapic reset flow
During ioapic reset, some registers need to be set to the default value
which defined in ioapic spec.

So far, the vioapic function only be called by ioapic itself in
ioapic_init. And just invoked after calloc the vioapic object, so all
the content are already set to zero. But this vioapic_reset function be
exported as one API which maybe invoked by other scenarios in future.

So this patch resolves this potential issue.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang 86de47b142 hv: vioapic: correct the ioapic id mask
The APIC ID field should be bit 24:27 in IOAPIC Identification register.
The bits 28:31 are reserved bits which need to be avoid touched.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang 68cbdb39de hv: vioapic: avoid deliver unnecessary interrupt for level trigger
For level sensitive trigger mode, the vioapic should not deliver extra
interrupt to vlapic if the previous one hasn't received EOI.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang 771c6db321 hv: vioapic: refine vioapic_mmio_rw function
Merge multiple if to switch-case. And set 0xFFFFFFFFU as the default
value of undefined address.

And the IOREGSEL register only bits 7:0 are defined, so mask the other
bits for read operation.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang f0d2291fe2 hv: vioapic: check vector prior to irr in EOI write emulation
Check the vector first to avoid unnecessary irr check.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang fc4162918a hv: vioapic: refine vioapic mmio access related code
1, Remove vioapic_mmio_read/vioapic_mmio_write, and combine them to
vioapic_mmio_rw.

2, The vioapic_read/write are used for emulate the ioapic indirect
access logic. So change their name with vioapic_indirect as the prefix.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yuan Liu 66814d8449 tools: fix resuming vm issue in acrnctl
This patch changes vm resuming condition from VM_STARTED to VM_PAUSED

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Yuhong Tao <yuhong.tao@intel.com>
Reviewed-by: Like Yan <like.yan@intel.com>
2018-08-06 12:29:20 +08:00
Yuan Liu 7b34ae84fa tools: fix resuming vm issue in acrnd
This patch resolves vm state mismatch between vm and acrnd
which causes vm resuming failure

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Yuhong Tao <yuhong.tao@intel.com>
Reviewed-by: Like Yan <like.yan@intel.com>
2018-08-06 12:29:20 +08:00
Yuan Liu 6cd6e3d3cc tools: fix an issue acrnd does not notify the vm stop state to cbc lifecycle service
This patch resolves acrnd does not notify vm stop state(suspend/shutdown) to
cbc_lifecycle after SOS enters suspend/shutdown, that causes cbc_lifecycle
cannot trigger SOS suspend/shutdown flow.

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Like Yan <like.yan@intel.com>
2018-08-06 12:29:20 +08:00
Yuan Liu 331300d8b9 tools: fix an invalid parameter of send_msg in query_state
The issue is "acrnctl list" command always returns error with "no vmname
provided" information.

The rootcause is that vmname is an invalid parameter, which does not contain
any vm information.

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Yuhong Tao <yuhong.tao@intel.com>
Reviewed-by: Like Yan <like.yan@intel.com>
2018-08-06 12:29:20 +08:00
Mingqiang Chi 7345677bbb hv:cleanup vmid related code
Remove structure vm_attr
Wrap two APIs alloc_vm_id and free_vm_id

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-06 12:27:53 +08:00
Yonghua Huang 2299926a88 HV: Refine 'hv_main()' function usage
'hv_main()' wraps several logic which has no dependencies
   each other(enable VMX, prepare to create service os VM..),
   in this case, split this function to make code logic clear.

   remove 'is_vm0_bsp()' & 'hv_main()'
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-06 10:34:43 +08:00
David B. Kinder 9d9c97d668 doc: fix table in acrn-shell documentation
Fix an indentation problem during in doc review.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-08-03 09:05:16 -07:00
yonghuah 093f2f9980 Update acrn-shell.rst 2018-08-03 08:38:19 -07:00
yonghuah 9689227665 Update acrn-shell.rst 2018-08-03 08:38:19 -07:00
yonghuah f9bf917a6a HV: Refine hypervisor shell commands
removed shell commands:
--vcpu_pause
--vcpu_resume
--lsreq
--(warm) reboot
--vcpu_dumpmem

updated shell commands:
--vm_console -> sos_console
--trigger crash -> reboot
--merge 'set_loglevel' & 'get_loglevel' to 'loglevel'

new adding shell commands:
--dumpmem --> dump host physical memory
2018-08-03 08:38:19 -07:00
Sainath Grandhi 6643adff8b HV: Adding mptable support for partition mode ACRN
Partitioning mode of ACRN needs to build mptable for UOS.
UOS uses mptable instead of ACPI tables.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-03 13:36:40 +08:00
Shiqing Gao fd0c9187ef hv: treewide: fix 'Procedure parameter has a type but no identifier'
Add the parameter identifier for typedef function pointer.

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-03 13:29:24 +08:00
Kaige Fu c27e25052b HV: instr_emul: Move op_byte from vie_op to instr_emul_vie
one/two_byte_opcodes is indexed by op_byte. So vie_op->op_byte is unnecessary.
This patch remove it and add a new variable opcode to instr_emul_vie.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-03 13:05:12 +08:00
Kaige Fu baf055ec21 HV: instr_emul: Using size2mask array directly
There are size2mask array to convert addsize to corresponding mask and function
vie_size2mask doing the same thing except validation check of addrsize.
Theoretically, addrsize can only be one of (1, 2, 4, 8). So, the check of addrsize
is unnecessary.

This patch remove vie_size2mask and use size2maks directly.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-03 13:05:12 +08:00
Kaige Fu b6a0a36cd1 HV: instr_emul: Remove vie_read_register
We have vm_set/get_register here. There is no need to wrap the function with
vie_read_register.

This patch remove it.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-08-03 13:05:12 +08:00
Arindam Roy 37026590c9 HV: Rename functions, variables starting with "_"
In order to comply with MISRA C rules, renamed vairables
and function names starting with "_".
The major changes invloves mostly static function
names, as they are being called inside the same file
by a wrapper function.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-08-03 12:49:01 +08:00
Shiqing Gao a71dedecd4 hv: treewide: fix 'Array has no bounds specified'
MISRAC requires that the array size should be declared explicitly.

This patch fixes the issues caused by the arrays that are defined in
link_ram.ld.in or assembly file.

v1 -> v2:
 * Update the solution based on the info from the following link.
   https://sourceware.org/binutils/docs/ld/Source-Code-Reference.html

   Fix pattern is like below:
   extern char start_of_ROM, end_of_ROM, start_of_FLASH;
   memcpy (& start_of_FLASH, & start_of_ROM, & end_of_ROM - &
start_of_ROM);

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-03 12:40:21 +08:00
Mingqiang Chi a3b44a2fa8 hv:Replace 0(cpu_id) with BOOT_CPU_ID
Replace 0(pcpu_id/vcpu_id) with BOOT_CPU_ID

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-03 11:27:52 +08:00
Yuan Liu 7a3d03c82d dm: uart: fix acrn-dm crash issue when invoke uart_closetty function
mevent is added only if uart backend fd refers TTY in uart_opentty.
So we should only delete mevent if uart backend fd refers TTY in uart_closetty.

This issue can be reproduced by below steps
1) acrnd starts UOS
2) run poweroff command in UOS
3) crash happens

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
2018-08-03 11:11:21 +08:00
Li, Fei1 8f39a22961 hv: cpu: remove unnecessary cpu_id valid check
Remove unnecessary cpu_id valid check if the cpu_id comes from
get_cpu_id().

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-02 15:21:34 +08:00
Edwin Zhai a98113bfce HV: fully check VMCS control settings
Reshuffle VMX init code, and check both allowed 0-settings and
1-settings of related MSR to make the final VMCS control value.

Signed-off-by: Edwin Zhai <edwin.zhai@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-02 14:54:00 +08:00
Mingqiang Chi ae8836d960 hv:fix return value violation for vioapic_get_rte
Change this API to void type
Add pre-condition, state the input parameters are not NULL.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 14:47:43 +08:00
Yonghua Huang cd3a62f89b HV: Refine invalid parameter handling in hypervisor shell
- print error message for command parameter error
   when callback/handler is called.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 14:34:30 +08:00
Mingqiang Chi 61782d7430 hv:Rename port/mmio read and write APIs
mmio_write_long --> mmio_write32
mmio_write_word --> mmio_write16
mmio_write_byte --> mmio_write8
mmio_read_long  --> mmio_read32
mmio_read_word  --> mmio_read16
mmio_read_byte  --> mmio_read8

io_write_long --> pio_write32
io_write_word --> pio_write16
io_write_byte --> pio_write8
io_read_long  --> pio_read32
io_read_word  --> pio_read16
io_read_byte  --> pio_read8
io_write      --> pio_write
io_read       --> pio_read

setl --> set32
setw --> set16
setb --> set8

igned-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-08-02 14:03:38 +08:00
Yin Fengwei 7db4c0aac9 DM: Add funciton to update PM_WAK_STS
According to ACPI spec, when system back to working mode from
S3, WAK_STS bit (15) should be set.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 13:14:03 +08:00
Yin Fengwei a8a27d82d0 dm: add S3 support for UOS
We do:
 - pause target vm
 - suspend all virtual devices
 - wait for resume notification
 - resume all virtual devices
 - reset target vm

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 13:14:03 +08:00
Yin Fengwei 8ee4c0b1dd DM: add vm_stop/reset_watchdog
When guest enter/exit S3, we need to do
1. stop watchdog timer when guest enter S3 to avoid watchdog
   timer reset guest when guest is in S3 state.
2. reset watchdog timer when guest exit from S3.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 13:14:03 +08:00
Yin Fengwei a2241d983d DM: register pm ops to monitor
Then, acrnctl could send command to monitor module of DM and call
functions defined in pm ops. One example is: acrnctl resume UOS
after UOS enter S3.

Also add general pm.c and move pm related function to this file.

Signed-off-by: Yan Like <like.yan@intel.com>
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 13:14:03 +08:00
Yin Fengwei f576f97ea8 hv: add vm restart API
And export the API to DM. DM will do system reboot/S3 resume based
on this API.

Also add the pre-assumption description for some vm APIs.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 13:14:03 +08:00
Yin Fengwei a4eebb0ef8 hv: cleanup inline assembly code in vmx.c a little bit
1. We could explicitly use specific register to avoid one more
   register allocated.
2. If we explicitly assign register, it's not neccessary to
   add the register in clobber list according to gcc mannual.
3. For vmptrld, we add memory to clobber list also.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Edwin Zhai <edwin.zhai@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 13:14:03 +08:00
Xiangyang Wu 77c3917544 HV:treewide:avoid using multiple # or ## in a macro
In the C99 standard, the order of evaluation associated with
multiple #, multiple ## or a mix of # and ## preprocessor
operator is unspecified. For this case, gcc 7.3.0 manual
does not specify related implementation. So it is unsafe
to use multiple # or ## in a macro.
BTW, there are some macros with one or more "##" which are
not used by hypervisor.

Update relate codes to avoid using multiple # or ## in a macro;
Remove unused macros with one or more "##";
Remove "struct __hack;" at the end of GETCC since it is useless.

Note:
     '##' operator usage constraints: A ## preprocessing token shall
     not occur at the beginning or at the end of a replacement list
     for either form of macro definition.
V1--V2:
	Update relate codes to avoid using multiple # or ## in a macro.
V2-->V3:
	Remove unused macros with one or more "##";
	Remove "struct __hack;" at the end of GETCC since it is useless.

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-02 13:10:16 +08:00
Sainath Grandhi 581a336bc8 HV: Add Partitioning mode option for ACRN
Adding Kconfig option to choose and compile partitioning mode for ACRN.
Current implementation does not allow ACRN to support sharing mode
and partitioning mode out of a single binary.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-02 12:58:09 +08:00
Mingqiang Chi 93ed0371a0 hv:cleanup console/uart code
-- Check uart enabled flag, it will return if the flag is false.
-- Add function declaration (uart16550_set_property) in console.h
-- Remove unnecessary function declaration(get_serial_handle)
-- Change uart_enabled and port_mapped to bool
-- Fix MISRA-C integer violations

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 11:25:40 +08:00