Commit Graph

240 Commits

Author SHA1 Message Date
Xiangyang Wu 3027bfab10 HV: treewide: enforce unsignedness of pcpu_id
In the hypervisor, physical cpu id is defined as "int" or "uint32_t"
type in the hypervisor. So there are some sign conversion issues
about  physical cpu id (pcpu_id) reported by static analysis tool.
Sign conversion violates the rules of MISRA C:2012.

In this patch, define physical cpu id as "uint16_t" type for all
modules in the hypervisor and change related codes. The valid
range of pcpu_id is 0~65534, INVALID_PCPU_ID is defined to the
invalid pcpu_id for error detection, BROADCAST_PCPU_ID is
broadcast pcpu_id used to notify all valid pcpu.

The type of pcpu_id in the struct vcpu and vcpu_id is "int" type,
this will be fixed in another patch.

V1-->V2:
    *  Change the type of pcpu_id from uint32_t to uint16_t;
    *  Define INVALID_PCPU_ID for error detection;
    *  Define BROADCAST_PCPU_ID to notify all valid pcpu.

V2-->V3:
    *  Update comments for INVALID_PCPU_ID and BROADCAST_PCPU_ID;
    *  Update addtional pcpu_id;
    *  Convert hexadecimals to unsigned to meet the type of pcpu_id;
    *  Clean up for MIN_PCPU_ID and MAX_PCPU_ID, they will be
       defined by configuration.
Note: fix bug in the init_lapic(), the pcpu_id shall be less than 8,
this is constraint by implement in the init_lapic().
Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-21 16:59:21 +08:00
Junjie Mao aa505a28bb HV: treewide: convert hexadecimals used in bitops to unsigned
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2018-06-21 13:12:39 +08:00
Huihuang Shi 23921384d0 HV:debug:fix "expression is not Boolean"
MISRA C explicit required expression should be boolean when
in branch statements (if,while...).

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-20 14:19:47 +08:00
Yan, Like 20b50ad4e8 HV: correct loglevel definitions and default values
1. remove duplicated definitions of mem_loglevel/console_loglevel;
2. Set default loglevels to display important messages:
 - CONSOLE_LOGLEVEL_DEFALUT is changed from 2 to 3;
 - MEM_LOGLEVEL_DEFAULT is changed from 4 to 5.

Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Yan, Like <like.yan@intel.com>
2018-06-20 13:23:46 +08:00
zhouji3x ad2d855302 hv: save registers on exception
This patch is for crashmode/ramdump. when exception occur:
1) save registers;
2) flush cache

Signed-off-by: zhouji3x <jianfengx.zhou@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-19 17:30:24 +08:00
Huihuang Shi 977c4b20b5 fix parted of "missing for discarded return value"
MISRA C required that return value should be used, missing for it should
add "(void)" prefix before the function call.
Some function can be declared without return value to avoid this problem.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-19 16:21:45 +08:00
zhouji3x 5f5c16dc15 hv: add shell command to trigger crash
this patch add shell command trigger crash for testing crashmode/ramdump

Signed-off-by: zhouji3x <jianfengx.zhou@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-19 15:32:04 +08:00
Yin Fengwei feed38f5ae hv: add suspend/resume callback for console
To handle s3 enter/exit for console

Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 13:41:45 +08:00
Jason Chen CJ 7aa3391d81 shell: refine shell function with copy_from_gva
using copy_from_gva for shell function shell_vcpu_dumpreg &
shell_vcpu_dumpmem

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-11 12:14:43 +08:00
Jason Chen CJ 4176042982 dump: refine dump.c with copy_from_gva
using copy_from_gva to do dump_guest_stack & show_guest_call_trace

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-11 12:14:43 +08:00
Junjie Mao c849bff850 HV: config: adapt to the generated config.h
This patch drops "#include <bsp_cfg.h>" and include the generated config.h in
CFLAGS for the configuration data.

Also make sure that all configuration data have the 'CONFIG_' prefix.

v4 -> v5:

    * No changes.

v3 -> v4:

    * Add '-include config.h' to hypervisor/bsp/uefi/efi/Makefile.
    * Update comments mentioning bsp_cfg.h.

v2 -> v3:

    * Include config.h on the command line instead of in any header or source to
      avoid including config.h multiple times.
    * Add config.h as an additional dependency for source compilation.

v1 -> v2:

    * No changes.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2018-06-08 17:21:13 +08:00
Huihuang Shi e591315a65 HV:treewide:C99-friendly per_cpu implementation change the per_cpu method
The current implementation of per_cpu relies on several non-c99 features,
and in additional involves arbitrary pointer arithmetic which is not MIS-
RA C friendly.

This patch introduces struct per_cpu_region which holds all the per_cpu
variables. Allocation of per_cpu data regions and access to per_cpu vari-
ables are greatly simplified, at the cost of making all per_cpu varaibl-
es accessible in files.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
2018-06-05 17:09:00 +08:00
Binbin Wu 9e7179c950 hv: support gva2gpa in different paging modes
Translate gva2gpa in different paging modes.
Change the definition of gva2gpa.
- return value for error status
- Add a parameter for error code when paging fault.
Change the definition of vm_gva2gpa.
- return value for error status
- Add a parameter for error code when paing fault.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-06-01 19:14:13 +08:00
Minggui Cao cd5d8c8da7 check UART valid or not when setup console timer
if no valid UART in hypervisor, not need setup console timer.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
2018-06-01 14:22:27 +08:00
David B. Kinder f4122d99c5 license: Replace license text with SPDX tag
Replace the BSD-3-Clause boiler plate license text with an SPDX tag.

Fixes: #189

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-06-01 10:43:06 +08:00
Kaige Fu 9af38e16e5 HV: Add log info when setup hvlog share buf
We have two sbuf for hvlog: one is allocated by hv for "early hvlog" and
the other one is allocated by SOS. Once SOS allocate the later one, the
hv allocated sbufs would be released after the contents being copied, we
call it sbuf switch.

And there is a trick here to guarantee that the switch of a certain per_cpu
sbuf is being done on exactly the certain physical CPU, that is doing the
switch at the first print after SOS allocated and setup its sbuf.

Because there are few logmsg within our current code, so will wait a bit long
for the next print. For ordinary case, it should be ok. However, for the
BTM(Boot Time Measurement) case, we need the content of "early hvlog" for
boot time calculation and it is not ok. So, we print those prints to force
the sbuf switch.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:49:09 +08:00
Zide Chen 8f16faab04 HV: further cleanup of header inclusions
According to the comments in hypervisor:
 " This file includes config header file "bsp_cfg.h" and other
	hypervisor used header files.
	It should be included in all the source files."

this patch includes all common header files in hypervisor.h
then removes other redundant inclusions

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-25 10:45:56 +08:00
Zide Chen d594878e31 HV: cleanup for header inclusions.
used https://gitlab.com/esr/deheader to detect and remove unnecessary
header file inclusions

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-25 10:45:56 +08:00
Mingqiang Chi 7c9cc6bcd4 hv:Merge dump_interrupt and dump_exception to a commond API
merge these two APIs to 'dump_intr_excp_frame'

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-23 13:38:52 +08:00
Mingqiang Chi d88b968305 hv: Remove nested check when dump exception
removed unnecessary nested check when dump exception

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-23 13:38:52 +08:00
Mingqiang Chi 8384ed2564 hv:rename data structure intr_ctx
rename intr_ctx to intr_excp_ctx

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-23 13:38:52 +08:00
Yin Fengwei 6ef48fa30e hv: Add reboot shell command
To trigger warm reboot for debugging.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>
2018-05-18 16:38:40 +08:00
Yin Fengwei 03a3fb0d2a hv: cleanup the shell cmd code.
Remove cmd register API. And use static pre-defined cmd array
instead.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>
2018-05-18 10:53:34 +08:00
Li, Fei1 edb26a7e17 hv: refine the left atomic operation
rename atomic_cmpxchg_int to atomic_cmpxchg
replace atomic_cmpset_long with atomic_cmpxchg64
rename atomic_readandclear_long to atomic_readandclear64

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2018-05-18 10:52:31 +08:00
Li, Fei1 1f3da93e74 hv: refine atomic_load/store_xxx name
rename atomic_load/store_xxx32 to atomic_load/store
rename atomic_load/store_xxx64 to atomic_load64/store64

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-18 10:52:31 +08:00
Li, Fei1 fadaf14a94 hv: refine atomic_xadd
1. rename atomic_xadd_int to atomic_xadd, add atomic_xadd64.
2. add atomic_add/sbu64_return, atomic_inc/dec64_return.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-18 10:52:31 +08:00
Li, Fei1 bd3f3b00f7 hv: fix incorrect use of atomic_set_xxx
1. vpic_wire_mode no need to atomically set its value.
2. uart open conut want to atomically set its value not atomically set
its bits.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-18 10:52:31 +08:00
Yonghua Huang 85716e8b01 security: fix issues reported by Klocwork
- NULL pointer reference risk
 - buffer overflow risk

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:57 +08:00
Li, Fei1 ac253f8c60 hv: timer: add periodic timer setup support
and add MIN_TIMER_PERIOD_US for limit periodic timer frequency.
Now it's set to 500 us.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:25:56 +08:00
Li, Fei1 9bfa574a27 hv: timer: restruct add_timer/del_timer API
add initialize_timer to initialize or reset a timer;
add_timer add timer to corresponding physical cpu timer list.
del_timer delete timer from corresponding physical cpu timer list.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:25:56 +08:00
Li, Fei1 be9f4ee9e6 hv: timer: pass timer callback function parameter by pointer
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Yan, Like 51a76a93fb hv: save early hv logmsg before sos booted
Add percpu earlylog sbuf within hypervisor memory space to accommodate log
before sos booting, and copy the earlylog to SOS allocated sbuf at the first
do_logmsg after SOS sets the sbuf during booting.

With the patch, earlylog of hypervisor could be captured with acrnlog
service if SOS booted. And it may help debugging hv issue if SOS failed to
boot, with "logdump" command.

Signed-off-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-05-15 17:25:55 +08:00
Zheng, Gen c5f860e1cb MMU: bug fix on operating va <=> pa convertion
Before referencing to physical address of devs such as lapic, ioapic,
vtd, and uart, switch to virtual address.
Use a phisical address of pml4 to write CR3.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:55 +08:00
Zheng, Gen d02f4d4a5f refine: change the address arguments type of mmio access api
Change the address arguments type of mmio access api from uint64_t
to void*.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:55 +08:00
Zheng, Gen 6b1782b360 refine: remove redundant data type definition
remove data defination of mmio_addr_t, vaddr_t, paddr_t,
and ioport_t.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:54 +08:00
yechunliang b11460f7f6 replace malloc and memset with calloc
malloc: allocate a block of memory, the contents of the block are undefined.
calloc: allocate a block of memory for an array of num elements and initializes all its bits to zero.

Signed-off-by: yechunliang <yechunliangcn@163.com>
2018-05-15 17:25:24 +08:00
Li, Fei1 ace23b5088 hv: shell: add cpuid command
Add cpuid shell command for test

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:25:24 +08:00
Qi Yadong 8d67f292ef Rename TIME_MS_DELTA to CYCLES_PER_MS
TIME_MS_DELTA is not clear enough, rename it to CYCLES_PER_MS.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-05-15 17:19:39 +08:00
Li, Fei1 36148041bc Move s[n]printf to lib for release
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:37 +08:00
Eddie Dong 7a3a539b17 initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-05-11 14:44:28 +08:00