When booting prelaunch RTVM with SSRAM enabled, we need to delete the
SSRAM region that is used by prelaunch RTVM from Service VM EPT mapping.
If it is not used, or it is not fully used, the SSRAM or the rest SSRAM
should be in Service VM map.
But current code has a issue that it always deletes all SSRAM region
from Service VM EPT, even when no SSRAM is enabled for prelaunch RTVM.
This could cause the post RTVM with SSRAM boot failure, as DM checks and
removes SSRAM region from Service VM EPT during post RTVM setup.
Changing get_software_sram_size() to PRE_RTVM_SW_SRAM_MAX_SIZE could
solve the issue, as PRE_RTVM_SW_SRAM_MAX_SIZE is the SSRAM size that
prelaunch RTVM actually uses.
Tracked-On: #7401
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
The movdqu instruction moves unaligned double quadword (128 bit)
contained in XMM registers.
This patch uses pointers as input parameters of the function
write_xmm_0_2() to get 128-bit value from 64-bit array for each XMM
register.
Tracked-On: #7380
Reviewed-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Jiang, Yanting <yanting.jiang@intel.com>
When enabling SRIOV capability for a PF in Service VM, ACRN Hypervisor
should add VF BARs mapping for PF since PF's firmware would access these
BARs to do initialization for VFs when it's first created.
Tracked-On: #4433
Signed-off-by: Fei Li <fei1.li@intel.com>
In spite of Table Size in MSI-X Message Control Register [Bits 10:0] masks as
RO (Register bits are read-only and cannot be altered by software), In Spec
PCIe 6.0, Chap 6.1.4.2 MSI-X Configuration "Depending upon system software
policy, system software, device driver software, or each at different times or
environments may configure a Function’s MSI-X Capability and table structures
with suitable vectors."
This patch just pass through MSI-X Control Register field to guest.
Tracked-On: #7275
Signed-off-by: Fei Li <fei1.li@intel.com>
Since CAT support for hybrid platform is landed, let's remove some old declarations
which are no longer used.
Tracked-On: #6690
Signed-off-by: Tw <wei.tan@intel.com>
Ignore the "scenario" and "board" field in <scenario>.xml:
<acrn-config board="whl-ipc-i5" scenario="shared">
Tracked-On: #7345
Signed-off-by: Conghui <conghui.chen@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
1. Support absolute path for scenario file.
2. Use the scenario xml file name as scenario name, but if it is
'scenario.xml', use the upper level directory name.
e.g.
SCENARIO=<pathxxx>/shared/scenario.xml
Then scenario name would be 'shared'.
3. Change 'realpath' to 'abspath' as we should keep the original path
for scenario file even it is a link file. This will make sure the
scenario name is always consistent with file set in 'SCENARIO='.
Tracked-On: #7345
Signed-off-by: Conghui <conghui.chen@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
The current code only supports 2 HPA regions per VM.
This patch extended ACRN to support 2+ HPA regions per VM, to use host
memory better if it is scatted among multiple regions.
This patch uses an array to describe the hpa region for the VM, and
change the logic of ve820 to support multiple regions.
This patch dependent on the config tool and GPA SSRAM change
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
When CPUID executes with EAX set to 1AH, the processor returns information about hybrid capabilities.
This information is percpu related, and should be obtained directly from the physical cpu.
Tracked-On: #6899
Signed-off-by: Tw <wei.tan@intel.com>
Page table entry present check is page table type
specific and static, e.g. just need to check bit0
of page entry for entries of MMU page table and
bit2~bit0 for EPT page table case. hence no need to
check it by callback function every time.
This patch remove 'pgentry_present' callback field and
add a new bitmask field for this page entry present check.
It can get better performance especially when this
check is executed frequently.
Tracked-On: #7327
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
When CPUID executes with EAX set to 02H, the processor returns information about cache and TLB information.
This information is percpu related, and should be obtained directly from the physical cpu.
BTW, this patch is backported from v2.7 branch.
Tracked-On: #6931
Signed-off-by: Tw <wei.tan@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
This patch is to eliminate a code scan warning.
p_elf_header32 was given a value when it was declared, but later it was
given the same value again. Just remove the later one.
Tracked-On: #7318
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Now interrupt vector in ACRN hypervisor is maintained as global variable, not
per-CPU variable. If there're more PCI devices, the physical interrupt vectors
are not enough most likely.
This patch would not allocate physical interrupt vector for MSI/MSI-X vectors
if interrupt posting could been used to inject the MSI/MSI-X interrupt to
a VM directly.
Tracked-On: #7275
Signed-off-by: Fei Li <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Using the SSRAM area size extracted by config_tools, the patch changes
the hard-coded GPA SSRAM area size to its actual size, so that
pre-launched VMs can support large(>8MB) SSRAM area.
When booting service VM, the SSRAM area has to be removed from Service
VM's mem space, because they are passed-through to the pre-rt VM. The
code was bugged since it was using the SSRAM area's GPA in the pre-rt
VM. Changed it to GPA in Service VM.
Tracked-On: #7212
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
On hybrid platform(e.g. ADL), there may be multiple instances of same level caches for different type of processors,
The current design only supports one global `rdt_info` for each RDT resource type.
In order to support hybrid platform, this patch introduce `rdt_ins` to represents the "instance".
Also, the number of `rdt_info` is dynamically generated by config-tool to match with physical board.
Tracked-On: projectacrn#6690
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
As RDT related information will be offered by config-tool dynamically,
and HV is just a consumer of that. So there's no need to do this detection
at startup anymore.
Tracked-On: projectacrn#6690
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
Many of the license and Intel copyright headers include the "All rights
reserved" string. It is not relevant in the context of the BSD-3-Clause
license that the code is released under. This patch removes those strings
throughout the code (hypervisor, devicemodel and misc).
Tracked-On: #7254
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
remove board and scenario attributes dependency for new configuration.
To do:
will remove board and scenario attributes in all scenario XML files
and update the upgrader.py after the new configuration works.
Tracked-On: #6690
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Now ACRN Hypervisor only support one PCI Segment, this patch add this check.
This patch also fix a small bug: it would trigger false error "DRHD with
INCLUDE_PCI_ALL flag is NOT the last one".
Tracked-On: #5907
Signed-off-by: Fei Li <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Now HI_MMIO_xxx is duplicate with MMIO64_xxx. This patch replace HI_MMIO_xxx
with MMIO64_xxx.
Tracked-On: #6011
Signed-off-by: Fei Li <fei1.li@intel.com>
Unify the handling of host/guest MSR area in VMCS. Remove the emum value
as the element index when there are a few of MSRs in host/guest area.
Because the index could be changed if one element not used. So, use a
variable to save the index which will be used.
Tracked-On: #6966
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Instead of using a Boolean variable indicating whether a build is for debug
or release, it is more intuitive to specify the build types as "debug" or
"release".
This patch converts the config item RELEASE to BUILD_TYPE which takes
"debug" or "release" as of now.
The generated header and makefile still uses RELEASE, and the command line
option RELEASE=<y or n> is also preserved.
Tracked-On: #6690
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Today the scripts that populate default values and validate scenarios have
different command-line interfaces: the former requires an XML schema as
input (which is cumbersome in most cases), while the latter always infer
where the XML schema is (which is inflexible).
This patch unifies the command line options of those scripts as follows:
- The scenario XML is always a required positional argument.
- The output file path (if any) is an optional positional argument.
- The schema XML file is an optional long option. When not specified, the
scripts will always use the one under the misc/config_tools/schema
directory.
Also, this patch makes the validator.py executable, as is done to other
executable scripts in the repo.
Tracked-On: #6690
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Requirement: in CPU partition VM (RTVM), vtune or perf can be used to
sample hotspot code path to tune the RT performance, It need support
PMU/PEBS (Processor Event Based Sampling). Intel TCC asks for it, too.
It exposes PEBS related capabilities/features and MSRs to CPU
partition VM, like RTVM. PEBS is a part of PMU. Also PEBS needs
DS (Debug Store) feature to support. So DS is exposed too.
Limitation: current it just support PEBS feature in VM level, when CPU
traps to HV, the performance counter will stop. Perf global control
MSR is used to do this work. So, the counters shall be close to native.
Tracked-On: #6966
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Add a flag: GUEST_FLAG_PMU_PASSTHROUGH to indicate if
PMU (Performance Monitor Unit) is passthrough to guest VM.
Tracked-On: #6966
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
NMI is used to notify LAPIC-PT RTVM, to kick its CPU into hypervisor.
But NMI could be used by system devices, like PMU (Performance Monitor
Unit). So use INIT signal as the partition CPU notification function, to
replace injecting NMI.
Also remove unused NMI as notification related code.
Tracked-On: #6966
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Now the vept module uses a mixture of nept and vept, it's better to
refine it.
So this patch rename nept to vept and simplify the interface of vept
init module.
Tracked-On: #6690
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Remove the fact that a default BOARD and SCENARIO are used in case there was
none provided by the user, nor any available from a previous build. Up until
now, if that was the case, a build was triggered using a default set of BOARD
and SCENARIO values. The 'make' command will now error out asking the user to
specify those parameters.
Tracked-On: #7112
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
This patch adds ENOTTY and ENOSYS to indicate undefined and obsoleted
request hyercall respectively, and uses ENOTTY as error code for undefined
hypercall instead of EINVAL to consistent with the ACRN kernel's return
value.
Tracked-On: #7029
Signed-off-by: Wen Qian <qian.wen@intel.com>
Signed-off-by: Li Fei <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The coding guideline rule C-ST-04 requires that
a 'if' statement followed by one or more 'else if'
statement shall be terminated by an 'else' statement
which contains either appropriate action or a comment.
Tracked-On: #6776
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Now the vept table was allocate dynamically, but the table size of vept
was calculated by the CONFIG_PLATFORM_RAM_SIZE which was predefined by
config tool.
It's not complete change and can't support single binary for different
boards/platforms.
So this patch will replace the CONFIG_PLATFORM_RAM_SIZE and get the
top ram size from hv_E820 interface for vept.
Tracked-On: #6690
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
Now the EPT module use predefined parameter "CONFIG_PLATFORM_RAM_SIZE"
to calculate the ept table size.
After change the EPT table to dynamic allocate to support single binary
for different boards/platforms, the ept table size should dynamic
calculate too.
So this patch replace CONFIG_PLATFORM_RAM_SIZE by the hv_e820_ram_size
to get the RAM info on run time.
Tracked-On: #6690
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
CONFIG_PLATFORM_RAM_SIZE is predefined by config tool and mmu use it to
calculate the table size and predefine the ppt table.
This patch will change the ppt to allocate dynamically and get the table
size by the hv_e820_ram_size interface which could get the RAM
info on run time and replace the CONFIG_PLATFORM_RAM_SIZE.
Tracked-On: #6690
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
The e820 module could get the RAM info on run time, but the RAM size
and MAX address was limited by CONFIG_PLATFORM_RAM_SIZE which was
predefined by config tool.
Current solution can't support single binary for different boards or
platforms and the CONFIG_PLATFORM_RAM_SIZE can't matching the RAM size
if user have not update config tools setting after the device changed.
So this patch remove the CONFIG_PLATFORM_RAM_SIZE and calculate ram
size on run time.
Tracked-On: #6690
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
The 'serial.conf' file need to be put in /etc/, but it is currently being
installed in $(libdir)/acrn/. We therefore ask the user to manually copy that
file over to the /etc/ folder. This patch fixes that by installing
'serial.conf' directly there.
Tracked-On: #7107
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Sometimes the memory to be allocated is not at the end of an entry,
that means we have to break one enty into 2 smaller entries, there
are two ways to add the new entry to hv_e820, adds to the end or
insert it.
The initial e820 table is ordered, that's why the e820_alloc_memory
interface asssum all entries was sorted, but add new entry to the
end will break the orde of hv_e820.
So we use insert_e820_entry to replace the add_e820_entry, the new
interfeac will keep the orde and users do not need sort again after
alloc region
Tracked-On: #6690
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Chenli Wei<chenli.wei@linux.intel.com>
HC_GET_PLATFORM_INFO hypercall is not supported anymore,
hence to remove related function and data structure definition.
Tracked-On: #6690
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Current mmu assum the high memory start from 4G,it's not true for some
platform.
The map logic use "high64_max_ram - 4G" to calculate the high ram size
without any check,it's an issue when the platform have no high memory.
So this patch add high64_min_ram variable to calculate the min address
of high memory and check the high64_min_ram to fix the previou issue.
Tracked-On: #6690
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
Today the XML validation logic is embedded in scenario_cfg_gen.py which is
highly entangled with the Python-internal representation of
configurations. Such representation is used by the current configurator,
but will soon be obsolete when the new configurator is introduced.
In order to avoid unnecessary work on this internal representation when we
refine the schema of scenario XML files, this patch separates the
validation logic into a new script which can either be used from the
command line or imported in other Python-based applications. At build time
this script will be used instead to validate the XML files given by users.
This change makes it easier to refine the current configuration items for
better developer experience.
Migration of existing checks in scenario_cfg_gen.py to XML schema will be
done by a following series.
v2 -> v3:
* Keep Invoking asl_gen.py to generate vACPI tables for pre-launched VMs.
v1 -> v2:
* Remove "all rights reserved" from the license header
* Upgrade the severity of the message indicating lack of xmlschema as
error according to our latest definitions of log severities, as
validation violations could indicate build time or boot time failures.
Tracked-On: #6690
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Today we assume the paths to the build directory do not contain the
character `@` and build the sed commands on top of this
assumption. However, there is no guarantee that this assumption holds.
This patch changes the separating character in sed pattern replacing
commands back to slash ('/') and escape the slashes in the replacements to
make the commands work. That gives more flexibility to the paths where
users can put their configuration files and build the project.
Tracked-On: #6691
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
The current code would inject GP to guest, when there's no IWKeyBackup,
and the guest tried to write MSR MSR_IA32_COPY_PLATFORM_TO_LOCAL(0xd92)
to copy IWKeyBackup for the platform to the IWKey for this logical processor.
This patch fixes it by adjusting the code logic, and it'll do nothing
instead of inject GP if no valid IWKeyBackup.
This patch alse add checking for the value being written to avoid setting
reserved MSR bits.
Tracked-On: #7018
Signed-off-by: Wen Qian <qian.wen@intel.com>
Signed-off-by: Li Fei <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Now the multiboot modules memory have not reserve,it's an issue if
these memory alloc and write before VM start.
Incorrect allocation of multiboot modules memory will cause VM lost
data or start faild.
So we find these modules memory range and reserve these memory from
e820 entry.
All these memory will realloc to VM which own them before the vm start.
Tracked-On: #6690
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
The coding guideline rule C-FN-16 requires that 'Mixed-use of
C code and assembly code in a single function shall not be allowed',
this patch wraps inline assembly to inline functions.
Tracked-On: #6776
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
v1-->v2:
use inline functions for read/write XMM registers
Rename `CONFIG_IOMMU_BUS_NUM` to `ACFG_MAX_PCI_BUS_NUM`. Configure tool
will calculate `ACFG_MAX_PCI_BUS_NUM` base on the max pci num which is
used by VF. So user needn't care about `ACFG_MAX_PCI_BUS_NUM`, and memory
will be used resonable.
Tracked-On: #6942
Signed-off-by: Yuanyuan Zhao <yuanyuan.zhao@linux.intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
remove is_valid_xsave_combination api,
assume the hardware or QEMU can guarantee that support
XSAVE on CPU side and XSAVE_XRSTR on VMX side or not.
will add offline-tool in QEMU platform to avoid the user
use wrong XSAVE configurations.
remov check VMX_PROCBASED_CTLS2_XSVE_XRSTR based on the above reason.
for VMX_PROCBASED_CTLS2_PAUSE_LOOP, now it will panic
if run ACRN over QEMU, here remove it from essential check,
and it will print error information when set this bit
if there is no the hardware capability.
v1-v2:
remove is_valid_xsave_combination
Tracked-On: #6584
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This patch adds an option CONFIG_KEEP_IRQ_DISABLED to hv (default n) and
config-tool so that when this option is 'y', all interrupts in hv root
mode will be permanently disabled.
With this option to be 'y', all interrupts received in root mode will be
handled in external interrupt vmexit after next VM entry. The postpone
latency is negligible. This new configuration is a requirement from x86
TEE's secure/non-secure interrupt flow support. Many race conditions can be
avoided when keeping IRQ off.
v5:
Rename CONFIG_ACRN_KEEP_IRQ_DISABLED to CONFIG_KEEP_IRQ_DISABLED
v4:
Change CPU_IRQ_ENABLE/DISABLE to
CPU_IRQ_ENABLE_ON_CONFIG/DISABLE_ON_CONFIG and guard them using
CONFIG_ACRN_KEEP_IRQ_DISABLED
v3:
CONFIG_ACRN_DISABLE_INTERRUPT -> CONFIG_ACRN_KEEP_IRQ_DISABLED
Add more comment in commit message
Tracked-On: #6571
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
"idle=halt " should be avoided in REE since we have to
keep the interrupt always masked in root mode.
Tracked-On: #6571
Signed-off-by: Jie Deng <jie.deng@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Helmut Buchsbaum