Pre-Launched VMs need the vbar_base values pre-populated
for pass-thru PCI devices.
This patch moves the pci parser logic from board_cfg_gen to library
so that scenario_cfg_gen scripts can use pci parser routines while
generating pci_dev file logical partition scenario.
Tracked-On: #4666
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Board config should relay on library/common.py and board_cfg_lib, then
remove the duplicate parameters and functions.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
This patch does the following
1) Removes the limitation on BAR size for 1 GB
2) Align the BAR address to the BAR size
Tracked-On: #4586
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. If the device configure space is not fixed by ACPI and its pbar address
is above 4G or lower than 2G, then remap the vbar address to high memory.
2. Due to GPU might have huge MMIO space which would result in
HV_RAM_SIZE overflow, skip its vBAR remapping for now when the size high
than 1GB.
Tracked-On: #4458
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Devices that support SR-IOV can expose their capabilities in
lspci -vv command as below. The offline tool, instead of picking
up the bios exposed memory region(bc000000) for the devices ends
picking up the SR-IOV memory region(00000000c0000000) and generates
VBAR address (in pci_devices.h). This is incorrect. This patch
fixes the offline tool to take the right memory region as the
VBAR address.
Sample lspic -vv log:
67:00.0 Ethernet controller: Intel Corporation Ethernet Connection
X722 for 10GbE backplane (rev 09)
Subsystem: Intel Corporation Device 0000
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
Latency: 0
Interrupt: pin A routed to IRQ 61
Region 0: Memory at bc000000 (64-bit, prefetchable) [size=16M]
Region 3: Memory at c1000000 (64-bit, prefetchable) [size=32K]
Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
IOVCap: Migration-, Interrupt Message Number: 000
IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+
IOVSta: Migration-
Initial VFs: 32, Total VFs: 32, Number of VFs: 0, Function Dependency Link: 00
VF offset: 16, stride: 1, Device ID: 37cd
Supported Page Size: 00000553, System Page Size: 00000001
Region 0: Memory at 00000000c0000000 (64-bit, prefetchable)
Region 3: Memory at 00000000c1020000 (64-bit, prefetchable)
VF Migration: offset: 00000000, BIR: 0
Tracked-On: #4443
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Currently MMIO BAR size not support size above 4G,
print warning to user to set the MMIO size in 4G region from BIOS.
Target-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Sometimes character '-' or space need to be converted to '_' to make string format uniformed.
Add this common api to satisfy such requirment and refine the code for board name generating.
Tracked-On: #3852
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Current python code could handle pci sub class name contain "-" as
expected, but some space characters may still exist. This patch support
to parse similar strings which contain "-" and ' ' for pci sub class name.
Also, add the index number as suffix for the similar strings
Tracked-On: #3788
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.the script will parse the the board information which already
generated, $(scenario).xml modified by user, generate scenario
vm configuration and apply to the acrn-hypervisor source code base.
2.parse cpu/memory/ttys/rootfs information from native os and store it to
the source code
3.implemnt scenario_config and it's usage
usage: scenario_cfg_gen.py --board <board_info_file> -scenario <scenario_info_file>
board_info_file : file name of the board info
scenario_info_file : file name of the scenario info
sample:
$ python3 scenario_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
Also improvement board config generate usage:
sample:
$ python3 board_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
V1-V2:
1). parse board_setting.xml was removed as these configuration will be
stitch into scenario configuration
2). parse console for different formats
3). parse epc sections
4). add logical partition rootfs
5). support to parse clos, while webui set to None type
6). support to parse bootargs, while webui set to nul
7). convert '-' to '_' for pci sub class name while generating source file
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
1. add misc.py to get systemd ram and root device
2. add more specify comments for arguments of functions
v1-v2:
typo: Parser -> Parse
some grammar check
v2-v3:
add the message for Cx state
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
the script will parser the the board information which already generated on
target board, and apply to the acrn-hypervisor as a patch.
usage: board_cfg_gen.py --board <board_info_file>
sample:
$ python3 board_cfg_gen.py --board ../target_board/board_info.xml
v1-v2:
1. allow to generate new board patch
v2-v3:
1. modify the description of generator tools
2. parser board_name.xml file
3. coding as PEP8 guildline
Tracked-On: #3480
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Shuang Zheng shuang.zheng@intel.com
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Sainath Grandhi