While the terms to refer to CPU topology levels are originally borrowed
from MSR listings in SDMs (i.e. thread, core, die and package), we now
align the topology information with the CPUID topology enumeration
leaf (which does not have a "package" level) in the
implementation. However, some hard-coded level types are not updated
accordingly, leading to strangely organized nodes in the generated board
XML.
This patch refines the CPU extractor of the board inspector by removing
such hard code. Also the XPATH counting the total number of threads is
refined to tolerate the variance of reported intermediate levels.
Tracked-On: #6689
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
MAXIMUM_PA_WIDTH will be calculated from board information.
Tracked-On: #6357
Signed-off-by: Liang Yi <yi.liang@intel.com>
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Add an xslt file "board_info.h.xsl". This file is used to
generate board_info.h which is used by hypervisor.
Tracked-On: #6024
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Junjie Mao