HV: add the missing brackets to loop body
MISRA-C requires the use of brackets, even when there is only one statement in the loop body. Signed-off-by: Ying Liu <ying2.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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df038fc0db
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fd81655e60
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@ -898,8 +898,9 @@ void ptdev_remove_msix_remapping(struct vm *vm, uint16_t virt_bdf,
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return;
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}
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for (i = 0; i < vector_count; i++)
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for (i = 0; i < vector_count; i++) {
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remove_msix_remapping(vm, virt_bdf, i);
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}
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}
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#ifdef HV_DEBUG
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@ -542,8 +542,9 @@ vioapic_reset(struct vioapic *vioapic)
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/* Initialize all redirection entries to mask all interrupts */
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pincount = vioapic_pincount(vioapic->vm);
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for (pin = 0U; pin < pincount; pin++)
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for (pin = 0U; pin < pincount; pin++) {
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vioapic->rtbl[pin].reg = MASK_ALL_INTERRUPTS;
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}
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}
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struct vioapic *
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@ -679,11 +679,13 @@ dump_isrvec_stk(struct vlapic *vlapic)
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struct lapic_reg *isrptr;
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isrptr = &vlapic->apic_page->isr[0];
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for (i = 0; i < 8; i++)
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for (i = 0; i < 8; i++) {
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printf("ISR%d 0x%08x\n", i, isrptr[i].val);
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}
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for (i = 0; i <= vlapic->isrvec_stk_top; i++)
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for (i = 0; i <= vlapic->isrvec_stk_top; i++) {
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printf("isrvec_stk[%d] = %d\n", i, vlapic->isrvec_stk[i]);
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}
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}
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/*
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@ -1511,11 +1513,13 @@ vlapic_reset(struct vlapic *vlapic)
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vlapic->svr_last = lapic->svr;
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for (i = 0; i < VLAPIC_MAXLVT_INDEX + 1; i++)
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for (i = 0; i < VLAPIC_MAXLVT_INDEX + 1; i++) {
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vlapic->lvt_last[i] = 0;
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}
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for (i = 0; i < ISRVEC_STK_SIZE; i++)
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for (i = 0; i < ISRVEC_STK_SIZE; i++) {
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vlapic->isrvec_stk[i] = 0;
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}
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vlapic->isrvec_stk_top = 0;
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}
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@ -1555,8 +1559,9 @@ void vlapic_restore(struct vlapic *vlapic, struct lapic_regs *regs)
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lapic->ppr = regs->ppr;
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lapic->ldr = regs->ldr;
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lapic->dfr = regs->dfr;
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for (i = 0; i < 8; i++)
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for (i = 0; i < 8; i++) {
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lapic->tmr[i].val = regs->tmr[i].val;
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}
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lapic->svr = regs->svr;
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vlapic_svr_write_handler(vlapic);
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lapic->lvt[APIC_LVT_TIMER].val = regs->lvt[APIC_LVT_TIMER].val;
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@ -1687,8 +1692,9 @@ vlapic_reset_tmr(struct vlapic *vlapic)
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic resetting all vectors to edge-triggered");
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for (vector = 0; vector <= 255; vector++)
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for (vector = 0; vector <= 255; vector++) {
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vlapic_set_tmr(vlapic, vector, false);
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}
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vcpu_make_request(vlapic->vcpu, ACRN_REQUEST_TMR_UPDATE);
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}
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@ -98,9 +98,10 @@ int create_vm(struct vm_description *vm_desc, struct vm **rtn_vm)
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goto err1;
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}
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for (id = 0U; id < (size_t)(sizeof(long) * 8U); id++)
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for (id = 0U; id < (size_t)(sizeof(long) * 8U); id++) {
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if (!bitmap_test_and_set(id, &vmid_bitmap))
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break;
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}
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vm->attr.id = id;
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vm->attr.boot_idx = id;
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@ -271,8 +272,9 @@ void pause_vm(struct vm *vm)
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vm->state = VM_PAUSED;
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foreach_vcpu(i, vm, vcpu)
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foreach_vcpu(i, vm, vcpu) {
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pause_vcpu(vcpu, VCPU_ZOMBIE);
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}
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}
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void resume_vm(struct vm *vm)
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@ -280,8 +282,9 @@ void resume_vm(struct vm *vm)
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uint16_t i;
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struct vcpu *vcpu = NULL;
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foreach_vcpu(i, vm, vcpu)
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foreach_vcpu(i, vm, vcpu) {
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resume_vcpu(vcpu);
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}
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vm->state = VM_STARTED;
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}
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@ -96,8 +96,9 @@ void init_msr_emulation(struct vcpu *vcpu)
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msr_bitmap = vcpu->vm->arch_vm.msr_bitmap;
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for (i = 0U; i < msrs_count; i++)
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for (i = 0U; i < msrs_count; i++) {
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enable_msr_interception(msr_bitmap, emulated_msrs[i]);
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}
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enable_msr_interception(msr_bitmap, MSR_IA32_PERF_CTL);
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@ -421,10 +421,11 @@ void suspend_ioapic(void)
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addr = map_ioapic(get_ioapic_base(ioapic_id));
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nr_pins = ioapic_nr_pins(addr);
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for (ioapic_pin = 0U; ioapic_pin < nr_pins; ioapic_pin++)
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for (ioapic_pin = 0U; ioapic_pin < nr_pins; ioapic_pin++) {
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ioapic_get_rte_entry(addr, ioapic_pin,
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&saved_rte[ioapic_id][ioapic_pin]);
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}
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}
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}
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void resume_ioapic(void)
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@ -437,10 +438,11 @@ void resume_ioapic(void)
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addr = map_ioapic(get_ioapic_base(ioapic_id));
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nr_pins = ioapic_nr_pins(addr);
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for (ioapic_pin = 0U; ioapic_pin < nr_pins; ioapic_pin++)
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for (ioapic_pin = 0U; ioapic_pin < nr_pins; ioapic_pin++) {
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ioapic_set_rte_entry(addr, ioapic_pin,
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&saved_rte[ioapic_id][ioapic_pin]);
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}
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}
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}
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#ifdef HV_DEBUG
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@ -31,8 +31,9 @@ static void init_irq_desc(void)
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spinlock_init(&irq_desc_base[i].irq_lock);
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}
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for (i = 0U; i <= NR_MAX_VECTOR; i++)
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for (i = 0U; i <= NR_MAX_VECTOR; i++) {
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vector_to_irq[i] = IRQ_INVALID;
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}
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}
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@ -151,8 +152,9 @@ static void _irq_desc_free_vector(uint32_t irq)
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if (vector_to_irq[vr] == irq)
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vector_to_irq[vr] = IRQ_INVALID;
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for (pcpu_id = 0U; pcpu_id < phys_cpu_num; pcpu_id++)
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for (pcpu_id = 0U; pcpu_id < phys_cpu_num; pcpu_id++) {
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per_cpu(irq_count, pcpu_id)[irq] = 0UL;
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}
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}
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static void disable_pic_irq(void)
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@ -188,8 +190,9 @@ irq_desc_append_dev(struct irq_desc *desc, void *node, bool share)
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added = false;
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} else {
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/* dev_list point to last valid node */
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while (dev_list->next != NULL)
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while (dev_list->next != NULL) {
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dev_list = dev_list->next;
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}
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/* add node */
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dev_list->next = node;
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}
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@ -235,8 +235,9 @@ static void iommu_flush_cache(struct dmar_drhd_rt *dmar_uint,
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if (iommu_ecap_c(dmar_uint->ecap) != 0U)
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return;
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for (i = 0U; i < size; i += CACHE_LINE_SIZE)
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for (i = 0U; i < size; i += CACHE_LINE_SIZE) {
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clflush((char *)p + i);
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}
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}
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#if DBG_IOMMU
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@ -1157,10 +1158,11 @@ void suspend_iommu(void)
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dmar_invalid_iotlb_global(dmar_unit);
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/* save IOMMU fault register state */
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for (i = 0U; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++)
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for (i = 0U; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++) {
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iommu_fault_state[iommu_idx][i] =
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iommu_read32(dmar_unit, DMAR_FECTL_REG +
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i * IOMMU_FAULT_REGISTER_STATE_NUM);
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}
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/* disable translation */
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dmar_disable_translation(dmar_unit);
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@ -1197,10 +1199,11 @@ void resume_iommu(void)
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dmar_invalid_iotlb_global(dmar_unit);
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/* restore IOMMU fault register state */
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for (i = 0U; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++)
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for (i = 0U; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++) {
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iommu_write32(dmar_unit, DMAR_FECTL_REG +
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i * IOMMU_FAULT_REGISTER_STATE_NUM,
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iommu_fault_state[iommu_idx][i]);
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}
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/* enable translation */
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dmar_enable_translation(dmar_unit);
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@ -118,8 +118,9 @@ biosacpi_search_rsdp(char *base, int length)
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strnlen_s(ACPI_SIG_RSDP, 8)) == 0) {
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cp = (uint8_t *)rsdp;
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sum = NULL;
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for (idx = 0; idx < RSDP_CHECKSUM_LENGTH; idx++)
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for (idx = 0; idx < RSDP_CHECKSUM_LENGTH; idx++) {
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sum += *(cp + idx);
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}
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if (sum != NULL)
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continue;
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