HV:Added support to perform MSR operation on all cpus
MSR operations are directly done based on physical cpu's profiling_handle_msrops: Per cpu function, performs the MSR operations (Read, Read clear,Write) For SOCWATCH/ power tool, generates MSR samples. profiling_msr_ops_all_cpus : Receives required information for MSR operations from guest, SMP calls profiling_handle_msrops, Copies the information collected to guest Tracked-On: projectacrn#1409 Acked-by: Eddie Dong <eddie.dong@intel.com> Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
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fc8f9d792c
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@ -211,12 +211,114 @@ static void profiling_disable_pmu(void)
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__func__, get_cpu_id());
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}
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/*
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* Read profiling data and transferred to SOS
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* Drop transfer of profiling data if sbuf is full/insufficient and log it
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*/
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static int profiling_generate_data(__unused int32_t collector, __unused uint32_t type)
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{
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/* to be implemented */
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return 0;
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}
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/*
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* Performs MSR operations - read, write and clear
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*/
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static void profiling_handle_msrops(void)
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{
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/* to be implemented */
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uint32_t i, j;
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struct profiling_msr_ops_list *my_msr_node
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= get_cpu_var(profiling_info.msr_node);
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struct sw_msr_op_info *sw_msrop
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= &(get_cpu_var(profiling_info.sw_msr_op_info));
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering cpu%d",
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__func__, get_cpu_id());
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if ((my_msr_node == NULL) ||
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(my_msr_node->msr_op_state != (int32_t)MSR_OP_REQUESTED)) {
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dev_dbg(ACRN_DBG_PROFILING, "%s: invalid my_msr_node on cpu%d",
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__func__, get_cpu_id());
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}
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if ((my_msr_node->num_entries == 0U) ||
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(my_msr_node->num_entries >= MAX_MSR_LIST_NUM)) {
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: invalid num_entries on cpu%d",
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__func__, get_cpu_id());
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return;
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}
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for (i = 0U; i < my_msr_node->num_entries; i++) {
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switch (my_msr_node->entries[i].msr_op_type) {
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case MSR_OP_READ:
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my_msr_node->entries[i].value
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= msr_read(my_msr_node->entries[i].msr_id);
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: MSRREAD cpu%d, msr_id=0x%x, msr_val=0x%llx",
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__func__, get_cpu_id(), my_msr_node->entries[i].msr_id,
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my_msr_node->entries[i].value);
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break;
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case MSR_OP_READ_CLEAR:
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my_msr_node->entries[i].value
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= msr_read(my_msr_node->entries[i].msr_id);
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: MSRREADCLEAR cpu%d, msr_id=0x%x, msr_val=0x%llx",
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__func__, get_cpu_id(), my_msr_node->entries[i].msr_id,
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my_msr_node->entries[i].value);
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msr_write(my_msr_node->entries[i].msr_id, 0U);
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break;
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case MSR_OP_WRITE:
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msr_write(my_msr_node->entries[i].msr_id,
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my_msr_node->entries[i].value);
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: MSRWRITE cpu%d, msr_id=0x%x, msr_val=0x%llx",
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__func__, get_cpu_id(), my_msr_node->entries[i].msr_id,
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my_msr_node->entries[i].value);
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break;
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default:
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pr_err("%s: unknown MSR op_type %u on cpu %d",
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__func__, my_msr_node->entries[i].msr_op_type,
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get_cpu_id());
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break;
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}
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}
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my_msr_node->msr_op_state = (int32_t)MSR_OP_HANDLED;
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/* Also generates sample */
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if ((my_msr_node->collector_id == COLLECT_POWER_DATA) &&
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(sw_msrop != NULL)) {
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sw_msrop->cpu_id = get_cpu_id();
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sw_msrop->valid_entries = my_msr_node->num_entries;
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/*
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* if 'param' is 0, then skip generating a sample since it is
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* an immediate MSR read operation.
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*/
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if (my_msr_node->entries[0].param == 0UL) {
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for (j = 0U; j < my_msr_node->num_entries; ++j) {
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sw_msrop->core_msr[j]
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= my_msr_node->entries[j].value;
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/*
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* socwatch uses the 'param' field to store the
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* sample id needed by socwatch to identify the
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* type of sample during post-processing
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*/
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sw_msrop->sample_id
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= my_msr_node->entries[j].param;
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}
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/* generate sample */
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(void)profiling_generate_data(COLLECT_POWER_DATA,
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SOCWATCH_MSR_OP);
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}
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my_msr_node->msr_op_state = (int32_t)MSR_OP_REQUESTED;
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}
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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}
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/*
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@ -325,12 +427,33 @@ void profiling_stop_pmu(void)
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/*
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* Performs MSR operations on all the CPU's
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*/
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int32_t profiling_msr_ops_all_cpus(__unused struct vm *vm, __unused uint64_t addr)
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int32_t profiling_msr_ops_all_cpus(struct vm *vm, uint64_t addr)
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{
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/* to be implemented
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* call to smp_call_function profiling_ipi_handler
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*/
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uint16_t i;
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struct profiling_msr_ops_list msr_list[phys_cpu_num];
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(void)memset((void *)&msr_list, 0U, sizeof(msr_list));
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering", __func__);
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if (copy_from_gpa(vm, &msr_list, addr, sizeof(msr_list)) != 0) {
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pr_err("%s: Unable to copy addr from vm\n", __func__);
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return -EINVAL;
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}
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for (i = 0U; i < phys_cpu_num; i++) {
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per_cpu(profiling_info.ipi_cmd, i) = IPI_MSR_OP;
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per_cpu(profiling_info.msr_node, i) = &(msr_list[i]);
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}
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smp_call_function(pcpu_active_bitmap, profiling_ipi_handler, NULL);
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if (copy_to_gpa(vm, &msr_list, addr, sizeof(msr_list)) != 0) {
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pr_err("%s: Unable to copy addr from vm\n", __func__);
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return -EINVAL;
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}
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting", __func__);
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return 0;
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}
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@ -18,6 +18,13 @@
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#define COLLECT_PROFILE_DATA 0
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#define COLLECT_POWER_DATA 1
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#define SOCWATCH_MSR_OP 100U
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enum MSR_CMD_STATUS {
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MSR_OP_READY = 0,
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MSR_OP_REQUESTED,
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MSR_OP_HANDLED
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};
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enum MSR_CMD_TYPE {
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MSR_OP_NONE = 0,
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MSR_OP_READ,
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@ -105,6 +112,13 @@ struct profiling_vm_info_list {
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struct profiling_vm_info vm_list[MAX_NR_VMS];
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};
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struct sw_msr_op_info {
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uint64_t core_msr[MAX_MSR_LIST_NUM];
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uint32_t cpu_id;
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uint32_t valid_entries;
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uint16_t sample_id;
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};
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struct profiling_msr_op {
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/* value to write or location to write into */
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uint64_t value;
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@ -116,6 +130,12 @@ struct profiling_msr_op {
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uint8_t reg_type;
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};
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struct profiling_msr_ops_list {
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int32_t collector_id;
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uint32_t num_entries;
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int32_t msr_op_state;
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struct profiling_msr_op entries[MAX_MSR_LIST_NUM];
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};
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struct profiling_pmi_config {
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uint32_t num_groups;
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uint32_t trigger_count;
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@ -185,9 +205,11 @@ struct sep_state {
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* Wrapper containing SEP sampling/profiling related data structures
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*/
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struct profiling_info_wrapper {
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struct profiling_msr_ops_list *msr_node;
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struct sep_state sep_state;
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ipi_commands ipi_cmd;
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socwatch_state soc_state;
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struct sw_msr_op_info sw_msr_op_info;
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} __aligned(8);
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int32_t profiling_get_version_info(struct vm *vm, uint64_t addr);
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