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dm: align bar base addr to PAGE_SIZE at least 

PCI spec said that BAR base should be naturally aligned. But on
ACRN if the bar size < PAGE_SIZE, BAR base should be aligned with
PAGE_SIZE. This is because the minimal size that EPT can map/unmap
is PAGE_SIZE.

Tracked-On: #5717
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Jian Jun Chen 2021-01-29 11:31:35 +08:00 committed by wenlingz
parent b7e360e5e5
commit fad6a94030
1 changed files with 8 additions and 0 deletions
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8
devicemodel/hw/pci/core.c
View File

@ -26,6 +26,7 @@
* $FreeBSD$
*/
#include <sys/user.h>
#include <errno.h>
#include <pthread.h>
#include <stdio.h>
@ -564,6 +565,13 @@ pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
return -1;
}
/* PCI spec said that BAR base should be naturally aligned. On ACRN
* if the bar size < PAGE_SIZE, BAR base should be aligned with
* PAGE_SIZE. This is because the minimal size that EPT can map/unmap
* is PAGE_SIZE.
*/
if (size < PAGE_SIZE)
size = PAGE_SIZE;
base = roundup2(*baseptr, size);
/* TODO:Currently, we only reserve gvt mmio regions,