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acrn-hypervisor
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HV: support vuart base & irq can be changed 

add two static variables for COM_BASE & COM_IRQ, to
support them dynamically changed.

Tracked-On: #2170
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Minggui Cao 2018-12-24 22:05:49 +08:00 committed by wenlingz
parent 537adaeb46
commit f4beaf501c
1 changed files with 12 additions and 14 deletions
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26
hypervisor/debug/vuart.c
View File

@ -33,6 +33,8 @@
#include "uart16550.h"
static uint8_t vuart_com_irq = CONFIG_COM_IRQ;
static uint16_t vuart_com_base = CONFIG_COM_BASE;
#ifndef CONFIG_PARTITION_MODE
static char vuart_rx_buf[RX_BUF_SIZE];
@ -111,8 +113,7 @@ static uint8_t vuart_intr_reason(const struct acrn_vuart *vu)
{
if (((vu->lsr & LSR_OE) != 0U) && ((vu->ier & IER_ELSI) != 0U)) {
return IIR_RLS;
} else if ((fifo_numchars(&vu->rxfifo) > 0U) &&
((vu->ier & IER_ERBFI) != 0U)) {
} else if ((fifo_numchars(&vu->rxfifo) > 0U) && ((vu->ier & IER_ERBFI) != 0U)) {
return IIR_RXTOUT;
} else if (vu->thre_int_pending && ((vu->ier & IER_ETBEI) != 0U)) {
return IIR_TXRDY;
@ -132,7 +133,7 @@ static void vuart_toggle_intr(const struct acrn_vuart *vu)
uint32_t operation;
intr_reason = vuart_intr_reason(vu);
vioapic_get_rte(vu->vm, CONFIG_COM_IRQ, &rte);
vioapic_get_rte(vu->vm, vuart_com_irq, &rte);
/* TODO:
* Here should assert vuart irq according to CONFIG_COM_IRQ polarity.
@ -143,15 +144,13 @@ static void vuart_toggle_intr(const struct acrn_vuart *vu)
* we want to make it as an known issue.
*/
if ((rte.full & IOAPIC_RTE_INTPOL) != 0UL) {
operation = (intr_reason != IIR_NOPEND) ?
GSI_SET_LOW : GSI_SET_HIGH;
operation = (intr_reason != IIR_NOPEND) ? GSI_SET_LOW : GSI_SET_HIGH;
} else {
operation = (intr_reason != IIR_NOPEND) ?
GSI_SET_HIGH : GSI_SET_LOW;
operation = (intr_reason != IIR_NOPEND) ? GSI_SET_HIGH : GSI_SET_LOW;
}
vpic_set_irq(vu->vm, CONFIG_COM_IRQ, operation);
vioapic_set_irq(vu->vm, CONFIG_COM_IRQ, operation);
vpic_set_irq(vu->vm, vuart_com_irq, operation);
vioapic_set_irq(vu->vm, vuart_com_irq, operation);
}
static void vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
@ -202,8 +201,7 @@ static void vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
fifo_reset(&vu->rxfifo);
}
vu->fcr = value_u8 &
(FCR_FIFOE | FCR_DMA | FCR_RX_MASK);
vu->fcr = value_u8 & (FCR_FIFOE | FCR_DMA | FCR_RX_MASK);
}
break;
case UART16550_LCR:
@ -323,7 +321,7 @@ static void vuart_register_io_handler(struct acrn_vm *vm)
{
struct vm_io_range range = {
.flags = IO_ATTR_RW,
.base = CONFIG_COM_BASE,
.base = vuart_com_base,
.len = 8U
};
@ -402,7 +400,7 @@ void vuart_init(struct acrn_vm *vm)
vm->vuart.dlh = (uint8_t)(divisor >> 8U);
vm->vuart.active = false;
vm->vuart.base = CONFIG_COM_BASE;
vm->vuart.base = vuart_com_base;
vm->vuart.vm = vm;
vuart_fifo_init(vu);
vuart_lock_init(vu);
@ -411,5 +409,5 @@ void vuart_init(struct acrn_vm *vm)
bool hv_used_dbg_intx(uint8_t intx_pin)
{
return is_dbg_uart_enabled() && (intx_pin == CONFIG_COM_IRQ);
return is_dbg_uart_enabled() && (intx_pin == vuart_com_irq);
}