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hv: apicv: improve the default apicv reset flow 

Two improvements:

Firstly, disable EOI VMEXIT for all vectors by default. Only the level
sensitive irq need to set it due to need emulate send EOI to vioapic to
clear Remote IRR bit.

Secondly, to clear RVI(Requesting virtual interrupt) and SVI(Servicing
virtual interrupt) bits.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Yu Wang 2018-07-30 09:35:49 +00:00 committed by lijinxia
parent 6e86d4841d
commit f42878ee3a
1 changed files with 8 additions and 7 deletions
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15
hypervisor/arch/x86/vmx.c
View File

@ -1391,14 +1391,15 @@ static void init_exec_ctrl(struct vcpu *vcpu)
value64);
if (is_vapic_intr_delivery_supported()) {
/* these fields are supported only on processors
* that support the 1-setting of the "virtual-interrupt
* delivery" VM-execution control
/* Disable all EOI VMEXIT by default and
* clear RVI and SVI.
*/
exec_vmwrite64(VMX_EOI_EXIT0_FULL, ~0UL);
exec_vmwrite64(VMX_EOI_EXIT1_FULL, ~0UL);
exec_vmwrite64(VMX_EOI_EXIT2_FULL, ~0UL);
exec_vmwrite64(VMX_EOI_EXIT3_FULL, ~0UL);
exec_vmwrite64(VMX_EOI_EXIT0_FULL, 0UL);
exec_vmwrite64(VMX_EOI_EXIT1_FULL, 0UL);
exec_vmwrite64(VMX_EOI_EXIT2_FULL, 0UL);
exec_vmwrite64(VMX_EOI_EXIT3_FULL, 0UL);
exec_vmwrite16(VMX_GUEST_INTR_STATUS, 0);
}
}