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dm:gvt:update bus0 memlimit32 value 

Now the GVT already tries to reserve the region.
the problem is that the region should be
reflected in PCI BUS0 memlimit32 and updated to DSDT table.

As the GVT PCI bar0/2 is in reserved region
and not updated to memlimit32 in DSDT table,
the problem is triggered.

Tracked-On: projectacrn#4227

Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Junming Liu 2019-12-11 14:06:23 +00:00 committed by wenlingz
parent acb5affd0b
commit f2bf3d3ed1
1 changed files with 19 additions and 1 deletions
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20
devicemodel/hw/pci/core.c
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@ -1376,9 +1376,10 @@ init_pci(struct vmctx *ctx)
struct slotinfo *si; struct slotinfo *si;
struct funcinfo *fi; struct funcinfo *fi;
size_t lowmem; size_t lowmem;
int bus, slot, func; int bus, slot, func, i;
int success_cnt = 0; int success_cnt = 0;
int error; int error;
uint64_t bus0_memlimit;
pci_emul_iobase = PCI_EMUL_IOBASE; pci_emul_iobase = PCI_EMUL_IOBASE;
pci_emul_membase32 = vm_get_lowmem_limit(ctx); pci_emul_membase32 = vm_get_lowmem_limit(ctx);
@ -1440,6 +1441,23 @@ init_pci(struct vmctx *ctx)
bi->memlimit64 = pci_emul_membase64; bi->memlimit64 = pci_emul_membase64;
} }
/* TODO: gvt PCI bar0 and bar2 aren't allocated by ACRN DM,
* here, need update bus0 memlimit32 value.
* Currently, we only deal with bus0 memlimit32.
* If other PCI devices also use reserved regions,
* need to change these code.
*/
bi = pci_businfo[0];
bus0_memlimit = bi->memlimit32;
for(i = 0; i < REGION_NUMS; i++){
if(reserved_bar_regions[i].vdev &&
reserved_bar_regions[i].bar_type == PCIBAR_MEM32){
bus0_memlimit = (bus0_memlimit > (reserved_bar_regions[i].end + 1))
? bus0_memlimit : (reserved_bar_regions[i].end + 1);
}
}
bi->memlimit32 = bus0_memlimit;
error = check_gsi_sharing_violation(); error = check_gsi_sharing_violation();
if (error < 0) if (error < 0)
goto pci_emul_init_fail; goto pci_emul_init_fail;