hv: remove pci_vdev_read_cfg_u8/16/32
reduce the use of similar APIs (particularly the name confusion) for CFG space read/write. Tracked-On: #4433 Signed-off-by: Yuan Liu <yuan1.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -41,13 +41,13 @@ uint32_t pci_vdev_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_
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switch (bytes) {
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switch (bytes) {
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case 1U:
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case 1U:
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val = pci_vdev_read_cfg_u8(vdev, offset);
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val = vdev->cfgdata.data_8[offset];
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break;
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break;
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case 2U:
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case 2U:
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val = pci_vdev_read_cfg_u16(vdev, offset);
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val = vdev->cfgdata.data_16[offset >> 1U];
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break;
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break;
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default:
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default:
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val = pci_vdev_read_cfg_u32(vdev, offset);
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val = vdev->cfgdata.data_32[offset >> 2U];
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break;
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break;
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}
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}
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@ -99,7 +99,7 @@ uint32_t pci_vdev_read_bar(const struct pci_vdev *vdev, uint32_t idx)
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uint32_t bar, offset;
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uint32_t bar, offset;
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offset = pci_bar_offset(idx);
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offset = pci_bar_offset(idx);
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bar = pci_vdev_read_cfg_u32(vdev, offset);
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bar = pci_vdev_read_cfg(vdev, offset, 4U);
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/* Sizing BAR */
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/* Sizing BAR */
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if (bar == ~0U) {
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if (bar == ~0U) {
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bar = vdev->vbars[idx].mask | vdev->vbars[idx].fixed;
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bar = vdev->vbars[idx].mask | vdev->vbars[idx].fixed;
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@ -117,14 +117,14 @@ static void pci_vdev_update_bar_base(struct pci_vdev *vdev, uint32_t idx)
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vbar = &vdev->vbars[idx];
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vbar = &vdev->vbars[idx];
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offset = pci_bar_offset(idx);
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offset = pci_bar_offset(idx);
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lo = pci_vdev_read_cfg_u32(vdev, offset);
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lo = pci_vdev_read_cfg(vdev, offset, 4U);
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if ((vbar->type != PCIBAR_NONE) && (lo != ~0U)) {
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if ((vbar->type != PCIBAR_NONE) && (lo != ~0U)) {
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type = vbar->type;
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type = vbar->type;
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base = lo & vbar->mask;
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base = lo & vbar->mask;
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if (vbar->type == PCIBAR_MEM64) {
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if (vbar->type == PCIBAR_MEM64) {
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vbar = &vdev->vbars[idx + 1U];
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vbar = &vdev->vbars[idx + 1U];
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hi = pci_vdev_read_cfg_u32(vdev, offset + 4U);
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hi = pci_vdev_read_cfg(vdev, (offset + 4U), 4U);
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if (hi != ~0U) {
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if (hi != ~0U) {
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hi &= vbar->mask;
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hi &= vbar->mask;
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base |= ((uint64_t)hi << 32U);
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base |= ((uint64_t)hi << 32U);
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@ -69,12 +69,12 @@ static void remap_vmsi(const struct pci_vdev *vdev)
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uint32_t vmsi_msgdata, vmsi_addrlo, vmsi_addrhi = 0U;
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uint32_t vmsi_msgdata, vmsi_addrlo, vmsi_addrhi = 0U;
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/* Read the MSI capability structure from virtual device */
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/* Read the MSI capability structure from virtual device */
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vmsi_addrlo = pci_vdev_read_cfg_u32(vdev, capoff + PCIR_MSI_ADDR);
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vmsi_addrlo = pci_vdev_read_cfg(vdev, (capoff + PCIR_MSI_ADDR), 4U);
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if (vdev->msi.is_64bit) {
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if (vdev->msi.is_64bit) {
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vmsi_addrhi = pci_vdev_read_cfg_u32(vdev, capoff + PCIR_MSI_ADDR_HIGH);
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vmsi_addrhi = pci_vdev_read_cfg(vdev, (capoff + PCIR_MSI_ADDR_HIGH), 4U);
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vmsi_msgdata = pci_vdev_read_cfg_u16(vdev, capoff + PCIR_MSI_DATA_64BIT);
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vmsi_msgdata = pci_vdev_read_cfg(vdev, (capoff + PCIR_MSI_DATA_64BIT), 2U);
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} else {
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} else {
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vmsi_msgdata = pci_vdev_read_cfg_u16(vdev, capoff + PCIR_MSI_DATA);
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vmsi_msgdata = pci_vdev_read_cfg(vdev, (capoff + PCIR_MSI_DATA), 2U);
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}
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}
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info.vmsi_addr.full = (uint64_t)vmsi_addrlo | ((uint64_t)vmsi_addrhi << 32U);
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info.vmsi_addr.full = (uint64_t)vmsi_addrlo | ((uint64_t)vmsi_addrhi << 32U);
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info.vmsi_data.full = vmsi_msgdata;
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info.vmsi_data.full = vmsi_msgdata;
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@ -37,30 +37,6 @@ static inline bool in_range(uint32_t value, uint32_t lower, uint32_t len)
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return ((value >= lower) && (value < (lower + len)));
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return ((value >= lower) && (value < (lower + len)));
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}
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}
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/**
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* @pre vdev != NULL
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*/
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static inline uint8_t pci_vdev_read_cfg_u8(const struct pci_vdev *vdev, uint32_t offset)
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{
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return vdev->cfgdata.data_8[offset];
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}
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/**
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* @pre vdev != NULL
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*/
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static inline uint16_t pci_vdev_read_cfg_u16(const struct pci_vdev *vdev, uint32_t offset)
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{
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return vdev->cfgdata.data_16[offset >> 1U];
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}
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/**
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* @pre vdev != NULL
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*/
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static inline uint32_t pci_vdev_read_cfg_u32(const struct pci_vdev *vdev, uint32_t offset)
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{
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return vdev->cfgdata.data_32[offset >> 2U];
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}
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/**
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/**
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* @pre vdev != NULL
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* @pre vdev != NULL
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*/
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*/
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