From f01aad7e779e5fed048b2a681224baebc84bb036 Mon Sep 17 00:00:00 2001 From: Sainath Grandhi Date: Tue, 8 Oct 2019 16:59:51 -0700 Subject: [PATCH] hv: Let trampoline execution use 1GB pages ACRN currently uses 2MB large pages in the page tables setup for trampoline code and data. This patch lets ACRN use 1GB large pages instead. When it comes to fixing symbols in trampoline code, fixing pointers in PDPT is no more needed as PDPT PTEs contain Physical Address. Tracked-On: #3899 Signed-off-by: Sainath Grandhi Acked-by: Eddie Dong --- hypervisor/arch/x86/boot/trampoline.S | 19 +++++-------------- hypervisor/arch/x86/trampoline.c | 9 +++------ 2 files changed, 8 insertions(+), 20 deletions(-) diff --git a/hypervisor/arch/x86/boot/trampoline.S b/hypervisor/arch/x86/boot/trampoline.S index f994402ad..8b67f4dee 100644 --- a/hypervisor/arch/x86/boot/trampoline.S +++ b/hypervisor/arch/x86/boot/trampoline.S @@ -179,7 +179,8 @@ trampoline_gdt_ptr: .short (trampoline_gdt_end - trampoline_gdt) - 1 .quad trampoline_gdt -/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */ +/* PML4 and PDPT tables initialized to map first 4 GBytes of memory */ +/* Assumes CPU supports 1GB large pages */ .align 4 .global cpu_boot_page_tables_ptr cpu_boot_page_tables_ptr: @@ -197,19 +198,9 @@ cpu_boot_page_tables_start: trampoline_pdpt_addr: address = 0 .rept 4 - /* 0x3 = (PAGE_PRESENT | PAGE_RW) */ - .quad trampoline_pdt_addr + address + 0x3 - /*0x1000 = PAGE_SIZE*/ - address = address + 0x1000 - .endr - /*0x1000 = PAGE_SIZE*/ - .align 0x1000 -trampoline_pdt_addr: - address = 0 - .rept 2048 - /* 0x83 = (PAGE_PSE | PAGE_PRESENT | PAGE_RW) */ - .quad address + 0x83 - address = address + 0x200000 + /* 0x83 = (PAGE_PRESENT | PAGE_PSE | PAGE_RW) */ + .quad address + 0x83 + address = address + 0x40000000 .endr .end diff --git a/hypervisor/arch/x86/trampoline.c b/hypervisor/arch/x86/trampoline.c index 96f5407cf..d2c8a8f25 100644 --- a/hypervisor/arch/x86/trampoline.c +++ b/hypervisor/arch/x86/trampoline.c @@ -59,11 +59,13 @@ uint64_t get_trampoline_start16_paddr(void) return trampoline_start16_paddr; } +/* + * @pre pcpu_has_cap(X86_FEATURE_PAGE1GB) == true + */ static void update_trampoline_code_refs(uint64_t dest_pa) { void *ptr; uint64_t val; - int32_t i; /* * calculate the fixup CS:IP according to fixup target address @@ -87,11 +89,6 @@ static void update_trampoline_code_refs(uint64_t dest_pa) ptr = hpa2hva(dest_pa + trampoline_relo_addr(&cpu_boot_page_tables_start)); *(uint64_t *)(ptr) += dest_pa; - ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_pdpt_addr)); - for (i = 0; i < 4; i++) { - *(uint64_t *)(ptr + sizeof(uint64_t) * i) += dest_pa; - } - /* update the gdt base pointer with relocated offset */ ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_gdt_ptr)); *(uint64_t *)(ptr + 2) += dest_pa;