hv: vcpuid: reduce the cyclomatic complexity of function guest_cpuid
This patch reduces the cyclomatic complexity of the function guest_cpuid. Tracked-On: #2834 Signed-off-by: Binbin Wu <binbin.wu@intel.com>
This commit is contained in:
Binbin Wu
Eddie Dong
parent
f0d06165d3
commit
ef19ed8961
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@ -294,13 +294,132 @@ int32_t set_vcpuid_entries(struct acrn_vm *vm)
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return result;
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}
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static inline bool is_percpu_related(uint32_t leaf)
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{
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return ((leaf == 0x1U) || (leaf == 0xbU) || (leaf == 0xdU));
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}
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static void guest_cpuid_01h(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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uint32_t apicid = vlapic_get_apicid(vcpu_vlapic(vcpu));
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cpuid(0x1U, eax, ebx, ecx, edx);
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/* Patching initial APIC ID */
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*ebx &= ~APIC_ID_MASK;
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*ebx |= (apicid << APIC_ID_SHIFT);
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if (vm_hide_mtrr(vcpu->vm)) {
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/* mask mtrr */
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*edx &= ~CPUID_EDX_MTRR;
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}
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/* mask Debug Store feature */
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*ecx &= ~(CPUID_ECX_DTES64 | CPUID_ECX_DS_CPL);
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/* mask Safer Mode Extension */
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*ecx &= ~CPUID_ECX_SMX;
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/* mask PDCM: Perfmon and Debug Capability */
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*ecx &= ~CPUID_ECX_PDCM;
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/* mask SDBG for silicon debug */
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*ecx &= ~CPUID_ECX_SDBG;
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/* mask pcid */
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*ecx &= ~CPUID_ECX_PCID;
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/*mask vmx to guest os */
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*ecx &= ~CPUID_ECX_VMX;
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/* set Hypervisor Present Bit */
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*ecx |= CPUID_ECX_HV;
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/*no xsave support for guest if it is not enabled on host*/
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if ((*ecx & CPUID_ECX_OSXSAVE) == 0U) {
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*ecx &= ~CPUID_ECX_XSAVE;
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}
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*ecx &= ~CPUID_ECX_OSXSAVE;
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if ((*ecx & CPUID_ECX_XSAVE) != 0U) {
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uint64_t cr4;
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/*read guest CR4*/
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cr4 = exec_vmread(VMX_GUEST_CR4);
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if ((cr4 & CR4_OSXSAVE) != 0UL) {
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*ecx |= CPUID_ECX_OSXSAVE;
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}
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}
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/* mask Debug Store feature */
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*edx &= ~CPUID_EDX_DTES;
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}
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static void guest_cpuid_0bh(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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uint32_t leaf = 0x0bU;
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uint32_t subleaf = *ecx;
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/* Patching X2APIC */
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if (is_lapic_pt(vcpu->vm)) {
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/* for VM with LAPIC_PT, eg. PRE_LAUNCHED_VM or POST_LAUNCHED_VM with LAPIC_PT*/
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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} else if (is_sos_vm(vcpu->vm)) {
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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} else {
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*ecx = subleaf & 0xFFU;
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*edx = vlapic_get_apicid(vcpu_vlapic(vcpu));
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/* No HT emulation for UOS */
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switch (subleaf) {
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case 0U:
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*eax = 0U;
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*ebx = 1U;
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*ecx |= (1U << 8U);
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break;
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case 1U:
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if (vcpu->vm->hw.created_vcpus == 1U) {
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*eax = 0U;
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} else {
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*eax = (uint32_t)fls32(vcpu->vm->hw.created_vcpus - 1U) + 1U;
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}
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*ebx = vcpu->vm->hw.created_vcpus;
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*ecx |= (2U << 8U);
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break;
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default:
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*eax = 0U;
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*ebx = 0U;
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*ecx |= (0U << 8U);
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break;
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}
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}
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}
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static void guest_cpuid_0dh(__unused struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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uint32_t subleaf = *ecx;
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if (!pcpu_has_cap(X86_FEATURE_OSXSAVE)) {
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*eax = 0U;
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*ebx = 0U;
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*ecx = 0U;
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*edx = 0U;
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} else {
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cpuid_subleaf(0x0dU, subleaf, eax, ebx, ecx, edx);
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if (subleaf == 0U) {
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/* SDM Vol.1 17-2, On processors that do not support Intel MPX,
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* CPUID.(EAX=0DH,ECX=0):EAX[3] and
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* CPUID.(EAX=0DH,ECX=0):EAX[4] will both be 0 */
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*eax &= ~ CPUID_EAX_XCR0_BNDREGS;
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*eax &= ~ CPUID_EAX_XCR0_BNDCSR;
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}
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}
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}
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void guest_cpuid(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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uint32_t leaf = *eax;
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uint32_t subleaf = *ecx;
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/* vm related */
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if ((leaf != 0x1U) && (leaf != 0xbU) && (leaf != 0xdU)) {
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if (!is_percpu_related(leaf)) {
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const struct vcpuid_entry *entry = find_vcpuid_entry(vcpu, leaf, subleaf);
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if (entry != NULL) {
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@ -318,110 +437,15 @@ void guest_cpuid(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t
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/* percpu related */
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switch (leaf) {
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case 0x01U:
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{
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cpuid(leaf, eax, ebx, ecx, edx);
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uint32_t apicid = vlapic_get_apicid(vcpu_vlapic(vcpu));
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/* Patching initial APIC ID */
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*ebx &= ~APIC_ID_MASK;
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*ebx |= (apicid << APIC_ID_SHIFT);
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if (vm_hide_mtrr(vcpu->vm)) {
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/* mask mtrr */
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*edx &= ~CPUID_EDX_MTRR;
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}
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/* mask Debug Store feature */
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*ecx &= ~(CPUID_ECX_DTES64 | CPUID_ECX_DS_CPL);
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/* mask Safer Mode Extension */
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*ecx &= ~CPUID_ECX_SMX;
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/* mask PDCM: Perfmon and Debug Capability */
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*ecx &= ~CPUID_ECX_PDCM;
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/* mask SDBG for silicon debug */
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*ecx &= ~CPUID_ECX_SDBG;
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/* mask pcid */
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*ecx &= ~CPUID_ECX_PCID;
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/*mask vmx to guest os */
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*ecx &= ~CPUID_ECX_VMX;
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/* set Hypervisor Present Bit */
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*ecx |= CPUID_ECX_HV;
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/*no xsave support for guest if it is not enabled on host*/
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if ((*ecx & CPUID_ECX_OSXSAVE) == 0U) {
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*ecx &= ~CPUID_ECX_XSAVE;
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}
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*ecx &= ~CPUID_ECX_OSXSAVE;
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if ((*ecx & CPUID_ECX_XSAVE) != 0U) {
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uint64_t cr4;
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/*read guest CR4*/
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cr4 = exec_vmread(VMX_GUEST_CR4);
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if ((cr4 & CR4_OSXSAVE) != 0UL) {
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*ecx |= CPUID_ECX_OSXSAVE;
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}
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}
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/* mask Debug Store feature */
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*edx &= ~CPUID_EDX_DTES;
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guest_cpuid_01h(vcpu, eax, ebx, ecx, edx);
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break;
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}
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case 0x0bU:
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/* Patching X2APIC */
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if (is_lapic_pt(vcpu->vm)) {
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/* for VM with LAPIC_PT, eg. PRE_LAUNCHED_VM or POST_LAUNCHED_VM with LAPIC_PT*/
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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} else if (is_sos_vm(vcpu->vm)) {
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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} else {
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*ecx = subleaf & 0xFFU;
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*edx = vlapic_get_apicid(vcpu_vlapic(vcpu));
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/* No HT emulation for UOS */
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switch (subleaf) {
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case 0U:
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*eax = 0U;
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*ebx = 1U;
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*ecx |= (1U << 8U);
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break;
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case 1U:
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if (vcpu->vm->hw.created_vcpus == 1U) {
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*eax = 0U;
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} else {
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*eax = (uint32_t)fls32(vcpu->vm->hw.created_vcpus - 1U) + 1U;
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}
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*ebx = vcpu->vm->hw.created_vcpus;
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*ecx |= (2U << 8U);
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break;
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default:
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*eax = 0U;
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*ebx = 0U;
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*ecx |= (0U << 8U);
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break;
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}
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}
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guest_cpuid_0bh(vcpu, eax, ebx, ecx, edx);
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break;
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case 0x0dU:
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if (!pcpu_has_cap(X86_FEATURE_OSXSAVE)) {
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*eax = 0U;
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*ebx = 0U;
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*ecx = 0U;
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*edx = 0U;
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} else {
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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if (subleaf == 0U) {
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/* SDM Vol.1 17-2, On processors that do not support Intel MPX,
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* CPUID.(EAX=0DH,ECX=0):EAX[3] and
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* CPUID.(EAX=0DH,ECX=0):EAX[4] will both be 0 */
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*eax &= ~ CPUID_EAX_XCR0_BNDREGS;
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*eax &= ~ CPUID_EAX_XCR0_BNDCSR;
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}
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}
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guest_cpuid_0dh(vcpu, eax, ebx, ecx, edx);
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break;
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default:
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