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acrn-hypervisor
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hv: some coding style fixes 

Fix issues reported by checkpatch.pl

Tracked-On: #5917
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
dongshen 2021-05-06 14:14:39 -07:00 committed by wenlingz
parent f7ef46f0d9
commit ebadf00de8
7 changed files with 20 additions and 25 deletions
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7
hypervisor/arch/x86/guest/vcpuid.c
View File

@ -61,8 +61,7 @@ static inline const struct vcpuid_entry *find_vcpuid_entry(const struct acrn_vcp
if ((leaf & 0x80000000U) != 0U) {
limit = vm->vcpuid_xlevel;
}
else {
} else {
limit = vm->vcpuid_level;
}
@ -90,7 +89,7 @@ static inline int32_t set_vcpuid_entry(struct acrn_vm *vm,
if (vm->vcpuid_entry_nr == MAX_VM_VCPUID_ENTRIES) {
pr_err("%s, vcpuid entry over MAX_VM_VCPUID_ENTRIES(%u)\n", __func__, MAX_VM_VCPUID_ENTRIES);
ret = -ENOMEM;
ret = -ENOMEM;
} else {
tmp = &vm->vcpuid_entries[vm->vcpuid_entry_nr];
vm->vcpuid_entry_nr++;
@ -248,7 +247,7 @@ static int32_t set_vcpuid_sgx(struct acrn_vm *vm)
if (is_vsgx_supported(vm->vm_id)) {
struct vcpuid_entry entry;
struct epc_map* maps;
struct epc_map *maps;
uint32_t mid;
uint64_t size = 0;
/* init cpuid.12h.0h */

6
hypervisor/arch/x86/guest/vmsr.c
View File

@ -234,8 +234,8 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
/*
* CET disabled:
* CPUID.07H.ECX[7] (CPUID_ECX_CET_SS)
* CPUID.07H.EDX[20] (CPUID_ECX_CET_IBT)
* CPUID.07H.ECX[7] (CPUID_ECX_CET_SS)
* CPUID.07H.EDX[20] (CPUID_ECX_CET_IBT)
*/
MSR_IA32_U_CET,
MSR_IA32_S_CET,
@ -699,7 +699,7 @@ static void set_guest_tsc_adjust(struct acrn_vcpu *vcpu, uint64_t tsc_adjust)
/* IA32_TSC_ADJUST is supposed to carry the value it's written to */
vcpu_set_guest_msr(vcpu, MSR_IA32_TSC_ADJUST, tsc_adjust);
set_tsc_msr_interception(vcpu, (tsc_offset + tsc_adjust_delta ) != 0UL);
set_tsc_msr_interception(vcpu, (tsc_offset + tsc_adjust_delta) != 0UL);
}
/**

3
hypervisor/arch/x86/rdt.c
View File

@ -216,9 +216,8 @@ bool is_platform_rdt_capable(void)
return ret;
}
#else
uint64_t clos2pqr_msr(uint16_t clos)
uint64_t clos2pqr_msr(__unused uint16_t clos)
{
(void)(clos);
return 0UL;
}

13
hypervisor/arch/x86/timer.c
View File

@ -19,7 +19,7 @@
#define CAL_MS 10U
#define MIN_TIMER_PERIOD_US 500U
static uint32_t tsc_khz = 0U;
static uint32_t tsc_khz;
uint64_t rdtsc(void)
{
@ -74,8 +74,7 @@ static bool local_add_timer(struct per_cpu_timers *cpu_timer,
tmp = container_of(pos, struct hv_timer, node);
if (tmp->fire_tsc < tsc) {
prev = &tmp->node;
}
else {
} else {
break;
}
}
@ -155,7 +154,7 @@ static void timer_softirq(uint16_t pcpu_id)
{
struct per_cpu_timers *cpu_timer;
struct hv_timer *timer;
struct list_head *pos, *n;
const struct list_head *pos, *n;
uint32_t tries = MAX_TIMER_ACTIONS;
uint64_t current_tsc = rdtsc();
@ -268,7 +267,7 @@ static uint64_t pit_calibrate_tsc(uint32_t cal_ms_arg)
static uint64_t native_calibrate_tsc(void)
{
uint64_t tsc_hz = 0UL;
struct cpuinfo_x86 *cpu_info = get_pcpu_info();
const struct cpuinfo_x86 *cpu_info = get_pcpu_info();
if (cpu_info->cpuid_level >= 0x15U) {
uint32_t eax_denominator, ebx_numerator, ecx_hz, reserved;
@ -284,6 +283,7 @@ static uint64_t native_calibrate_tsc(void)
if ((tsc_hz == 0UL) && (cpu_info->cpuid_level >= 0x16U)) {
uint32_t eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
cpuid_subleaf(0x16U, 0x0U, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
tsc_hz = (uint64_t) eax_base_mhz * 1000000U;
}
@ -294,6 +294,7 @@ static uint64_t native_calibrate_tsc(void)
void calibrate_tsc(void)
{
uint64_t tsc_hz;
tsc_hz = native_calibrate_tsc();
if (tsc_hz == 0U) {
tsc_hz = pit_calibrate_tsc(CAL_MS);
@ -321,7 +322,7 @@ uint64_t ticks_to_us(uint64_t ticks)
{
uint64_t us = 0UL;
if (tsc_khz != 0U ) {
if (tsc_khz != 0U) {
us = (ticks * 1000UL) / (uint64_t)tsc_khz;
}

6
hypervisor/debug/profiling.c
View File

@ -440,7 +440,7 @@ static int32_t profiling_generate_data(int32_t collector, uint32_t type)
ret = -1;
break;
}
if (ret == -1){
if (ret == -1) {
return 0;
}
pkt_header.payload_size = payload_size;
@ -683,8 +683,7 @@ static void profiling_pmi_handler(uint32_t irq, __unused void *data)
if (msrop->msr_id != MSR_IA32_PERF_GLOBAL_CTRL) {
msr_write(msrop->msr_id, msrop->value);
}
}
else {
} else {
if (((perf_ovf_status >> msrop->param) & 0x1U) > 0U) {
msr_write(msrop->msr_id, msrop->value);
}
@ -1391,6 +1390,7 @@ void profiling_setup(void)
{
uint16_t cpu;
int32_t retval;
dev_dbg(DBG_LEVEL_PROFILING, "%s: entering", __func__);
cpu = get_pcpu_id();
/* support PMI notification, SOS_VM will register all CPU */

5
hypervisor/debug/shell.c
View File

@ -1368,11 +1368,8 @@ static int32_t shell_cpuid(int32_t argc, char **argv)
return 0;
}
static int32_t shell_reboot(int32_t argc, char **argv)
static int32_t shell_reboot(__unused int32_t argc, __unused char **argv)
{
(void)argc;
(void)argv;
reset_host();
return 0;
}

5
hypervisor/dm/vpci/vhostbridge.c
View File

@ -117,11 +117,10 @@ static void init_vhostbridge(struct pci_vdev *vdev)
* and UOS_VIRT_PCI_MMCFG_BASE(0xE0000000) is fine. The trailing 1 is a ECAM enable-bit
*/
pciexbar_low = UOS_VIRT_PCI_MMCFG_BASE | 0x1U;
}
else {
} else {
/*Inject physical ECAM value to SOS vhostbridge since SOS may check PCIe-MMIO Base Address with it */
phys_did = pci_pdev_read_cfg(hostbridge_bdf, PCIR_DEVICE, 2);
for (i = 0U; i < (sizeof(hostbridge_did_highbytes) / sizeof(uint32_t)); i++){
for (i = 0U; i < (sizeof(hostbridge_did_highbytes) / sizeof(uint32_t)); i++) {
if (((phys_did & 0xff00U) >> 8) == hostbridge_did_highbytes[i]) {
/* The offset of PCIEXBAR register is 0x60 on Intel platforms, and no counter-case is encountered yet */
pciexbar_low = pci_pdev_read_cfg(hostbridge_bdf, 0x60U, 4);