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HV: Remove RDT code if CONFIG_RDT_ENABLED flag 

is not set

This patch does the following,
1. Removes RDT code if CONFIG_RDT_ENABLED flag is
not set.
2. Set the CONFIG_RDT_ENABLED flag only on platforms
that support RDT so that build scripts will automatically
reflect the config.

Tracked-On: #3715
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Vijay Dhanraj 2020-02-19 23:28:34 -08:00 committed by wenlingz
parent d0665fe220
commit eaad91fd71
17 changed files with 46 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hypervisor/arch/x86/configs/apl-mrb.config
View File

@ -7,3 +7,4 @@ CONFIG_PLATFORM_RAM_SIZE=0x200000000
CONFIG_SOS_RAM_SIZE=0x200000000
CONFIG_UOS_RAM_SIZE=0x200000000
CONFIG_IOMMU_BUS_NUM=0x10
CONFIG_RDT_ENABLED=n

4
hypervisor/arch/x86/configs/apl-mrb/board.c
View File

@ -14,8 +14,12 @@
#endif
struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM] = {

1
hypervisor/arch/x86/configs/apl-up2.config
View File

@ -3,3 +3,4 @@ CONFIG_BOARD="apl-up2"
CONFIG_SERIAL_PCI=y
CONFIG_SERIAL_PCI_BDF="0:18.0"
CONFIG_HV_RAM_START=0x5e000000
CONFIG_RDT_ENABLED=n

2
hypervisor/arch/x86/configs/apl-up2/board.c
View File

@ -16,6 +16,7 @@
struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM] = {
{
@ -35,6 +36,7 @@ struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM] = {
.msr_index = MSR_IA32_L2_MASK_BASE + 3U,
},
};
#endif
const struct cpu_state_table board_cpu_state_tbl;

1
hypervisor/arch/x86/configs/dnv-cb2.config
View File

@ -2,3 +2,4 @@
CONFIG_BOARD="dnv-cb2"
CONFIG_SERIAL_LEGACY=y
CONFIG_SERIAL_PIO_BASE=0x1000
CONFIG_RDT_ENABLED=n

4
hypervisor/arch/x86/configs/dnv-cb2/board.c
View File

@ -14,7 +14,11 @@
#endif
struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

1
hypervisor/arch/x86/configs/generic.config
View File

@ -1,3 +1,4 @@
# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
CONFIG_BOARD="generic"
CONFIG_SERIAL_LEGACY=y
CONFIG_RDT_ENABLED=n

4
hypervisor/arch/x86/configs/generic/board.c
View File

@ -14,7 +14,11 @@
#endif
struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

1
hypervisor/arch/x86/configs/icl-rvp.config
View File

@ -3,3 +3,4 @@ CONFIG_BOARD="icl-rvp"
CONFIG_SERIAL_LEGACY=y
CONFIG_SOS_RAM_SIZE=0x600000000
CONFIG_UOS_RAM_SIZE=0x600000000
CONFIG_RDT_ENABLED=n

4
hypervisor/arch/x86/configs/icl-rvp/board.c
View File

@ -14,7 +14,11 @@
#endif
struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

1
hypervisor/arch/x86/configs/nuc6cayh.config
View File

@ -5,3 +5,4 @@ CONFIG_BOARD="nuc6cayh"
CONFIG_SERIAL_PCI=y
CONFIG_SERIAL_PCI_BDF="0:18.0"
CONFIG_HV_RAM_START=0x20000000
CONFIG_RDT_ENABLED=n

4
hypervisor/arch/x86/configs/nuc6cayh/board.c
View File

@ -14,7 +14,11 @@
#endif
struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

1
hypervisor/arch/x86/configs/nuc7i7dnb.config
View File

@ -2,3 +2,4 @@
CONFIG_BOARD="nuc7i7dnb"
CONFIG_SERIAL_LEGACY=y
CONFIG_HV_RAM_START=0x60000000
CONFIG_RDT_ENABLED=n

3
hypervisor/arch/x86/configs/nuc7i7dnb/board.c
View File

@ -56,7 +56,10 @@ struct dmar_info plat_dmar_info = {
.drhd_units = drhd_info_array,
};
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
const struct cpu_state_table board_cpu_state_tbl;
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

2
hypervisor/arch/x86/cpu.c
View File

@ -262,9 +262,11 @@ void init_pcpu_post(uint16_t pcpu_id)
init_sched(pcpu_id);
#ifdef CONFIG_RDT_ENABLED
if (!setup_clos(pcpu_id)) {
panic("CLOS resource MSRs setup incorrectly!");
}
#endif
enable_smep();

8
hypervisor/arch/x86/rdt.c
View File

@ -42,6 +42,7 @@ const uint16_t hv_clos = 0U;
*/
const uint16_t platform_clos_num = MAX_PLATFORM_CLOS_NUM;
#ifdef CONFIG_RDT_ENABLED
static void rdt_read_cat_capability(int res)
{
uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
@ -158,6 +159,13 @@ uint64_t clos2pqr_msr(uint16_t clos)
return pqr_assoc;
}
#else
uint64_t clos2pqr_msr(uint16_t clos)
{
(void)(clos);
return 0UL;
}
#endif
bool is_platform_rdt_capable(void)
{

4
hypervisor/include/arch/x86/board.h
View File

@ -20,8 +20,12 @@ struct platform_clos_info {
};
extern struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
extern struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
extern struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
extern const struct cpu_state_table board_cpu_state_tbl;
extern const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];