hv: use asm_pause() to replace inline ASM to satisfy MISRAC
pause_cpu() --> asm_pause() hlt_cpu() --> asm_hlt() inline ASM pause --> asm_pause() Tracked-On: #1821 Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -301,7 +301,7 @@ void stop_cpus(void)
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void cpu_do_idle(void)
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{
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__asm __volatile("pause" ::: "memory");
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asm_pause();
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}
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/**
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@ -325,7 +325,7 @@ void cpu_dead(void)
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/* Halt the CPU */
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do {
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hlt_cpu();
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asm_hlt();
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} while (halt != 0);
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} else {
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pr_err("pcpu%hu already dead", pcpu_id);
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@ -578,7 +578,7 @@ void pause_vcpu(struct acrn_vcpu *vcpu, enum vcpu_state new_state)
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if (vcpu->pcpu_id != pcpu_id) {
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while (atomic_load32(&vcpu->running) == 1U)
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__asm__ __volatile("pause" ::: "memory");
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asm_pause();
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}
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} else {
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remove_from_cpu_runqueue(&vcpu->sched_obj, vcpu->pcpu_id);
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@ -256,7 +256,7 @@ static inline void dmar_wait_completion(const struct dmar_drhd_rt *dmar_unit, ui
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}
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ASSERT(((rdtsc() - start) < CYCLES_PER_MS),
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"DMAR OP Timeout!");
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pause_cpu();
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asm_pause();
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}
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}
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@ -247,7 +247,7 @@ void asm_assert(int32_t line, const char *file, const char *txt)
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show_host_call_trace(rsp, rbp, pcpu_id);
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dump_guest_context(pcpu_id);
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do {
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pause_cpu();
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asm_pause();
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} while (1);
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}
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@ -306,12 +306,12 @@ static inline void cpu_msr_write(uint32_t reg, uint64_t msr_val)
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asm volatile (" wrmsr " : : "c" (reg), "a" ((uint32_t)msr_val), "d" ((uint32_t)(msr_val >> 32U)));
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}
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static inline void pause_cpu(void)
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static inline void asm_pause(void)
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{
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asm volatile ("pause" ::: "memory");
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}
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static inline void hlt_cpu(void)
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static inline void asm_hlt(void)
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{
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asm volatile ("hlt");
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}
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@ -6,6 +6,7 @@
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#ifndef LOGMSG_H
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#define LOGMSG_H
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#include <cpu.h>
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/* Logging severity levels */
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#define LOG_FATAL 1U
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@ -116,6 +117,6 @@ void vprintf(const char *fmt, va_list args);
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#define panic(...) \
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do { pr_fatal("PANIC: %s line: %d\n", __func__, __LINE__); \
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pr_fatal(__VA_ARGS__); \
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while (1) { asm volatile ("pause" ::: "memory"); }; } while (0)
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while (1) { asm_pause(); }; } while (0)
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#endif /* LOGMSG_H */
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