HV: nuc7i7dnb example of new VM configuratons layout
There are 3 kinds of configurations in ACRN hypervisor source code: hypervisor
overall setting, per-board setting and scenario specific per-VM setting.
Currently Kconfig act as hypervisor overall setting and its souce is located at
"hypervisor/arch/x86/configs/$(BOARD).config"; Per-board configs are located at
"hypervisor/arch/x86/configs/$(BOARD)" folder; scenario specific per-VM configs
are located at "hypervisor/scenarios/$(SCENARIO)" folder.
This layout brings issues that board configs and VM configs are coupled tightly.
The board specific Kconfig file and misc_cfg.h are shared by all scenarios, and
scenario specific pci_dev.c is shared by all boards. So the user have no way to
build hypervisor binary for different scenario on different board with one
source code repo.
The patch will setup a new VM configurations layout as below:
misc/vm_configs
├── boards --> folder of supported boards
│ ├── <board_1> --> scenario-irrelevant board configs
│ │ ├── board.c --> C file of board configs
│ │ ├── board_info.h --> H file of board info
│ │ ├── pci_devices.h --> pBDF of PCI devices
│ │ └── platform_acpi_info.h --> native ACPI info
│ ├── <board_2>
│ ├── <board_3>
│ └── <board...>
└── scenarios --> folder of supported scenarios
├── <scenario_1> --> scenario specific VM configs
│ ├── <board_1> --> board specific VM configs for <scenario_1>
│ │ ├── <board_1>.config --> Kconfig for specific scenario on specific board
│ │ ├── misc_cfg.h --> H file of board specific VM configs
│ │ ├── pci_dev.c --> board specific VM pci devices list
│ │ └── vbar_base.h --> vBAR base info of VM PT pci devices
│ ├── <board_2>
│ ├── <board_3>
│ ├── <board...>
│ ├── vm_configurations.c --> C file of scenario specific VM configs
│ └── vm_configurations.h --> H file of scenario specific VM configs
├── <scenario_2>
├── <scenario_3>
└── <scenario...>
The new layout would decouple board configs and VM configs completely:
The boards folder stores kinds of supported boards info, each board folder
stores scenario-irrelevant board configs only, which could be totally got from
a physical platform and works for all scenarios;
The scenarios folder stores VM configs of kinds of working scenario. In each
scenario folder, besides the generic scenario specific VM configs, the board
specific VM configs would be put in a embedded board folder.
In new layout, all configs files will be removed out of hypervisor folder and
moved to a separate folder. This would make hypervisor LoC calculation more
precisely with below fomula:
typical LoC = Loc(hypervisor) + Loc(one vm_configs)
which
Loc(one vm_configs) = Loc(misc/vm_configs/boards/<board>)
+ LoC(misc/vm_configs/scenarios/<scenario>/<board>)
+ Loc(misc/vm_configs/scenarios/<scenario>/vm_configurations.c
+ Loc(misc/vm_configs/scenarios/<scenario>/vm_configurations.h
Tracked-On: #5077
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Victor Sun
wenlingz
parent
4ffa6cc7b1
commit
e792fa3d3c
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@ -30,7 +30,7 @@ extern struct dmar_info plat_dmar_info;
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#ifdef CONFIG_RDT_ENABLED
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extern struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
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extern struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
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extern struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
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extern struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
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#endif
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extern const struct cpu_state_table board_cpu_state_tbl;
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@ -7,7 +7,7 @@
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#ifndef PAGE_H
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#define PAGE_H
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#include <pci_devices.h>
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#include <board_info.h>
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#define PAGE_SHIFT 12U
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#define PAGE_SIZE (1U << PAGE_SHIFT)
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@ -31,14 +31,14 @@
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* - Guest OS won't re-program device MMIO bars to the address not covered by
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* this EPT_ADDRESS_SPACE.
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*/
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#define EPT_ADDRESS_SPACE(size) ((size > MEM_2G) ? \
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#define EPT_ADDRESS_SPACE(size) (((size) > MEM_2G) ? \
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((size) + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE) \
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: (MEM_2G + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE))
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#define PTDEV_HI_MMIO_START ((CONFIG_UOS_RAM_SIZE > MEM_2G) ? \
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(CONFIG_UOS_RAM_SIZE + PLATFORM_LO_MMIO_SIZE) : (MEM_2G + PLATFORM_LO_MMIO_SIZE))
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#define PRE_VM_EPT_ADDRESS_SPACE(size) (PTDEV_HI_MMIO_START + PTDEV_HI_MMIO_SIZE)
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#define PRE_VM_EPT_ADDRESS_SPACE(size) (PTDEV_HI_MMIO_START + HI_MMIO_SIZE)
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#define TOTAL_EPT_4K_PAGES_SIZE (PRE_VM_NUM*(PT_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))*MEM_4K)) + \
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(SOS_VM_NUM*(PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))*MEM_4K)) + \
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@ -1,65 +0,0 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm_config.h>
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#include <vuart.h>
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#include <pci_dev.h>
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struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
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{ /* VM0 */
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CONFIG_SOS_VM,
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.name = "ACRN SOS VM",
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/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
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.guest_flags = 0UL,
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.memory = {
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.start_hpa = 0UL,
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.size = CONFIG_SOS_RAM_SIZE,
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},
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.os_config = {
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.name = "ACRN Service OS",
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.kernel_type = KERNEL_BZIMAGE,
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.kernel_mod_tag = "Linux_bzImage",
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.bootargs = SOS_VM_BOOTARGS,
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},
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.vuart[0] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = SOS_COM1_BASE,
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.irq = SOS_COM1_IRQ,
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},
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.vuart[1] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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},
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},
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{ /* VM1 */
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CONFIG_POST_STD_VM(1),
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.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
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.vuart[0] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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},
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.vuart[1] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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}
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},
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#if CONFIG_MAX_KATA_VM_NUM > 0
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{ /* VM2 */
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CONFIG_KATA_VM(1),
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.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
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.vuart[0] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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},
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.vuart[1] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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}
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},
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#endif
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};
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@ -1,45 +0,0 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VM_CONFIGURATIONS_H
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#define VM_CONFIGURATIONS_H
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#include <misc_cfg.h>
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/* SOS_VM_NUM can only be 0U or 1U;
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* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
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* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
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*/
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#define PRE_VM_NUM 0U
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#define SOS_VM_NUM 1U
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#define MAX_POST_VM_NUM 2U /* including 1 KATA VM */
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#define CONFIG_MAX_KATA_VM_NUM 1U
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/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
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#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
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GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
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#define SOS_VM_BOOTARGS SOS_ROOTFS \
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"rw rootwait " \
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"console=tty0 " \
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SOS_CONSOLE \
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"consoleblank=0 " \
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"no_timer_check " \
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"quiet loglevel=3 " \
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"i915.nuclear_pageflip=1 " \
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"i915.avail_planes_per_pipe=0x01010F " \
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"i915.domain_plane_owners=0x011111110000 " \
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"i915.enable_gvt=1 " \
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SOS_IDLE \
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SOS_BOOTARGS_DIFF
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#if CONFIG_MAX_KATA_VM_NUM > 0
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#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
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#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U))
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#else
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#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
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#endif
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#endif /* VM_CONFIGURATIONS_H */
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@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOARD_INFO_H
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#define BOARD_INFO_H
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#define MAX_PCPU_NUM 4U
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#define MAX_PLATFORM_CLOS_NUM 0U
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#define MAX_MBA_CLOS_NUM_ENTRIES 0U
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#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
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#define MAX_HIDDEN_PDEVS_NUM 0U
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#define HI_MMIO_START ~0UL
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#define HI_MMIO_END 0UL
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#define HI_MMIO_SIZE 0x0UL
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#endif /* BOARD_INFO_H */
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@ -9,18 +9,12 @@
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#define PTDEV_HI_MMIO_SIZE 0xe00000UL
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#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}, \
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.vbar_base[0] = PTDEV_HI_MMIO_START + 0x200000UL, \
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.vbar_base[1] = PTDEV_HI_MMIO_START + 0x400000UL, \
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.vbar_base[5] = PTDEV_HI_MMIO_START + 0x600000UL
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#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}
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#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}, \
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.vbar_base[0] = PTDEV_HI_MMIO_START + 0x800000UL
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#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}
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#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1fU, .f = 0x06U}, \
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.vbar_base[0] = PTDEV_HI_MMIO_START + 0xa00000UL
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#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1fU, .f = 0x06U}
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#define NETWORK_CONTROLLER_0 .pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U}, \
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.vbar_base[0] = PTDEV_HI_MMIO_START + 0xc00000UL
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#define NETWORK_CONTROLLER_0 .pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U}
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#endif /* PCI_DEVICES_H_ */
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@ -7,10 +7,6 @@
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#ifndef MISC_CFG_H
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#define MISC_CFG_H
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#define MAX_PCPU_NUM 4U
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#define MAX_PLATFORM_CLOS_NUM 0U
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#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
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#define ROOTFS_0 "root=/dev/sda3 "
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#define ROOTFS_1 "root=/dev/nvme0n1p3 "
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@ -27,10 +23,4 @@
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#define SOS_BOOTARGS_DIFF ""
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#endif
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#define MAX_HIDDEN_PDEVS_NUM 0U
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#define HI_MMIO_START ~0UL
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#define HI_MMIO_END 0UL
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#endif /* MISC_CFG_H */
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@ -0,0 +1,26 @@
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/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MISC_CFG_H
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#define MISC_CFG_H
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#define ROOTFS_0 "root=/dev/sda3 "
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#define ROOTFS_1 "root=/dev/nvme0n1p3 "
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#define SOS_ROOTFS ROOTFS_0
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#define SOS_CONSOLE "console=ttyS0 "
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#define SOS_COM1_BASE 0x3F8U
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#define SOS_COM1_IRQ 4U
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#define SOS_COM2_BASE 0x2F8U
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#define SOS_COM2_IRQ 3U
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#ifndef CONFIG_RELEASE
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#define SOS_BOOTARGS_DIFF "hvlog=2M@0xE00000 memmap=0x200000$0xE00000 "
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#else
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#define SOS_BOOTARGS_DIFF ""
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#endif
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#endif /* MISC_CFG_H */
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@ -0,0 +1,5 @@
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# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
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CONFIG_BOARD="nuc7i7dnb"
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CONFIG_SERIAL_LEGACY=y
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CONFIG_HV_RAM_START=0x41000000
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CONFIG_RDT_ENABLED=n
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@ -0,0 +1,10 @@
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MISC_CFG_H
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#define MISC_CFG_H
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#endif /* MISC_CFG_H */
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@ -0,0 +1,5 @@
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# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
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CONFIG_BOARD="nuc7i7dnb"
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CONFIG_SERIAL_LEGACY=y
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CONFIG_HV_RAM_START=0x41000000
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CONFIG_RDT_ENABLED=n
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@ -7,13 +7,11 @@
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#include <vm_config.h>
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#include <pci_devices.h>
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#include <vpci.h>
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#include <vbar_base.h>
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#include <mmu.h>
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#include <page.h>
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/* The vbar_base info of pt devices is included in device MACROs which defined in
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* arch/x86/configs/$(CONFIG_BOARD)/pci_devices.h.
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* The memory range of vBAR should exactly match with the e820 layout of VM.
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*/
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#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR
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struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
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{
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@ -24,12 +22,12 @@ struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
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{
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.emu_type = PCI_DEV_TYPE_PTDEV,
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.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
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VM0_STORAGE_CONTROLLER
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PTDEV(SATA_CONTROLLER_0),
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},
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{
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.emu_type = PCI_DEV_TYPE_PTDEV,
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.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
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VM0_NETWORK_CONTROLLER
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PTDEV(ETHERNET_CONTROLLER_0),
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},
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};
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@ -42,13 +40,11 @@ struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM] = {
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{
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.emu_type = PCI_DEV_TYPE_PTDEV,
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.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
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VM1_STORAGE_CONTROLLER
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PTDEV(USB_CONTROLLER_0),
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},
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#if defined(VM1_NETWORK_CONTROLLER)
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{
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.emu_type = PCI_DEV_TYPE_PTDEV,
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.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
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VM1_NETWORK_CONTROLLER
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PTDEV(NETWORK_CONTROLLER_0),
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},
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#endif
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};
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@ -0,0 +1,44 @@
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VBAR_BASE_H_
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#define VBAR_BASE_H_
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#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0xde000000UL, \
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.vbar_base[2] = 0xc0000000UL
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#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0xdf252000UL
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#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf230000UL
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#define SIGNAL_PROCESSING_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf251000UL
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#define SIGNAL_PROCESSING_CONTROLLER_1_VBAR .vbar_base[0] = 0xdf250000UL
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#define SIGNAL_PROCESSING_CONTROLLER_2_VBAR .vbar_base[0] = 0xdf24f000UL
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#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf24e000UL
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#define SERIAL_CONTROLLER_0_VBAR .vbar_base[1] = 0xdf24d000UL
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#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf248000UL, \
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.vbar_base[1] = 0xdf24c000UL, \
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.vbar_base[5] = 0xdf24b000UL
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#define MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf244000UL
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#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = 0xdf240000UL, \
|
||||
.vbar_base[4] = 0xdf220000UL
|
||||
|
||||
#define SMBUS_0_VBAR .vbar_base[0] = 0xdf24a000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf200000UL
|
||||
|
||||
#define NETWORK_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf100000UL
|
||||
|
||||
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf000000UL
|
||||
|
||||
#endif /* VBAR_BASE_H_ */
|
||||
Loading…
Reference in New Issue