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acrn-config: fix build issue for TGL/EHL 

There is some macro defined in misc_cfg.h while CAT/MBA enabled.
include the missing header to solve build issue.

Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Wei Liu 2020-07-25 16:22:59 +08:00 committed by wenlingz
parent 3daf277c86
commit e37f857453
3 changed files with 4 additions and 3 deletions
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1
misc/acrn-config/board_config/board_c.py
View File

@ -19,6 +19,7 @@ INCLUDE_HEADER = """
#include <vtd.h>
#include <msr.h>
#include <pci.h>
#include <misc_cfg.h>
"""
MSR_IA32_L2_MASK_BASE = 0x00000D10

4
misc/acrn-config/board_config/misc_cfg_h.py
View File

@ -231,12 +231,12 @@ def generate_file(config):
mba_delay_list = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "MBA_DELAY")
idx = 0
for mba_delay_mask in mba_delay_list:
print("#define MBA_MASK_{}\t{}U".format(idx, mba_delay_mask), file=config)
print("#define MBA_MASK_{}\t\t\t{}U".format(idx, mba_delay_mask), file=config)
idx += 1
idx = 0
for cat_mask in cat_mask_list:
print("#define CLOS_MASK_{}\t{}U".format(idx, cat_mask), file=config)
print("#define CLOS_MASK_{}\t\t\t{}U".format(idx, cat_mask), file=config)
idx += 1
print("", file=config)

2
misc/acrn-config/scenario_config/vm_configurations_h.py
View File

@ -49,7 +49,7 @@ def clos_config_output(scenario_items, i, config):
if board_cfg_lib.is_rdt_supported() and hv_info.features.rdt_enabled == 'y':
clos_config = vm_info.get_clos_bitmap(i)
print("#define VM{0}_VCPU_CLOS\t\t{1}".format(i, clos_config['clos_map']), file=config)
print("#define VM{0}_VCPU_CLOS\t\t\t{1}".format(i, clos_config['clos_map']), file=config)
def scenario_vm_num(scenario_items, config):