hv: cpu: fix "Procedure has more than one exit point"
IEC 61508,ISO 26262 standards highly recommend single-exit rule. Reduce the count of the "return entries". Fix the violations which is comply with the cases list below: 1.Function has 2 return entries. 2.The first return entry is used to return the error code of checking variable whether is valid. Fix the violations in "if else" format. Tracked-On: #861 Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi
wenlingz
parent
7f08ad8375
commit
ddb548367a
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@ -67,12 +67,15 @@ bool cpu_has_cap(uint32_t bit)
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{
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uint32_t feat_idx = bit >> 5U;
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uint32_t feat_bit = bit & 0x1fU;
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bool ret;
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if (feat_idx >= FEATURE_WORDS) {
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return false;
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ret = false;
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} else {
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ret = ((boot_cpu_data.cpuid_leaves[feat_idx] & (1U << feat_bit)) != 0U);
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}
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return ((boot_cpu_data.cpuid_leaves[feat_idx] & (1U << feat_bit)) != 0U);
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return ret;
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}
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static inline bool get_monitor_cap(void)
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@ -710,22 +713,21 @@ void cpu_dead(uint16_t pcpu_id)
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*/
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int halt = 1;
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if (bitmap_test_and_clear_lock(pcpu_id, &pcpu_active_bitmap) == false) {
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if (bitmap_test_and_clear_lock(pcpu_id, &pcpu_active_bitmap)) {
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/* clean up native stuff */
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vmx_off(pcpu_id);
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cache_flush_invalidate_all();
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/* Set state to show CPU is dead */
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cpu_set_current_state(pcpu_id, PCPU_STATE_DEAD);
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/* Halt the CPU */
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do {
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hlt_cpu();
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} while (halt != 0);
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} else {
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pr_err("pcpu%hu already dead", pcpu_id);
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return;
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}
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/* clean up native stuff */
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vmx_off(pcpu_id);
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cache_flush_invalidate_all();
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/* Set state to show CPU is dead */
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cpu_set_current_state(pcpu_id, PCPU_STATE_DEAD);
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/* Halt the CPU */
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do {
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hlt_cpu();
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} while (halt != 0);
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}
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static void set_current_cpu_id(uint16_t pcpu_id)
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@ -804,15 +806,13 @@ static void ept_cap_detect(void)
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msr_val = msr_val >> 32U;
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/* Check if secondary processor based VM control is available. */
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if ((msr_val & VMX_PROCBASED_CTLS_SECONDARY) == 0UL) {
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return;
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}
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if ((msr_val & VMX_PROCBASED_CTLS_SECONDARY) != 0UL) {
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/* Read secondary processor based VM control. */
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msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS2);
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/* Read secondary processor based VM control. */
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msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS2);
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if (is_ctrl_setting_allowed(msr_val, VMX_PROCBASED_CTLS2_EPT)) {
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cpu_caps.ept_features = 1U;
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if (is_ctrl_setting_allowed(msr_val, VMX_PROCBASED_CTLS2_EPT)) {
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cpu_caps.ept_features = 1U;
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}
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}
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}
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@ -63,22 +63,24 @@ static inline struct vcpuid_entry *find_vcpuid_entry(const struct acrn_vcpu *vcp
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return entry;
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}
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static inline int set_vcpuid_entry(struct acrn_vm *vm,
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static inline int32_t set_vcpuid_entry(struct acrn_vm *vm,
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const struct vcpuid_entry *entry)
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{
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struct vcpuid_entry *tmp;
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size_t entry_size = sizeof(struct vcpuid_entry);
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int32_t ret;
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if (vm->vcpuid_entry_nr == MAX_VM_VCPUID_ENTRIES) {
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pr_err("%s, vcpuid entry over MAX_VM_VCPUID_ENTRIES(%u)\n",
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__func__, MAX_VM_VCPUID_ENTRIES);
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return -ENOMEM;
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ret = -ENOMEM;
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} else {
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tmp = &vm->vcpuid_entries[vm->vcpuid_entry_nr];
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vm->vcpuid_entry_nr++;
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(void)memcpy_s(tmp, entry_size, entry, entry_size);
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ret = 0;
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}
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tmp = &vm->vcpuid_entries[vm->vcpuid_entry_nr];
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vm->vcpuid_entry_nr++;
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(void)memcpy_s(tmp, entry_size, entry, entry_size);
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return 0;
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return ret;
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}
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/**
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@ -320,102 +322,100 @@ void guest_cpuid(struct acrn_vcpu *vcpu,
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*ecx = 0U;
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*edx = 0U;
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}
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return;
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}
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/* percpu related */
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switch (leaf) {
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case 0x01U:
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{
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cpuid(leaf, eax, ebx, ecx, edx);
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uint32_t apicid = vlapic_get_apicid(vcpu_vlapic(vcpu));
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/* Patching initial APIC ID */
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*ebx &= ~APIC_ID_MASK;
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*ebx |= (apicid << APIC_ID_SHIFT);
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} else {
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/* percpu related */
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switch (leaf) {
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case 0x01U:
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{
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cpuid(leaf, eax, ebx, ecx, edx);
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uint32_t apicid = vlapic_get_apicid(vcpu_vlapic(vcpu));
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/* Patching initial APIC ID */
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*ebx &= ~APIC_ID_MASK;
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*ebx |= (apicid << APIC_ID_SHIFT);
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#ifndef CONFIG_MTRR_ENABLED
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/* mask mtrr */
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*edx &= ~CPUID_EDX_MTRR;
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/* mask mtrr */
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*edx &= ~CPUID_EDX_MTRR;
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#endif
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/* mask pcid */
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*ecx &= ~CPUID_ECX_PCID;
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/* mask pcid */
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*ecx &= ~CPUID_ECX_PCID;
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/*mask vmx to guest os */
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*ecx &= ~CPUID_ECX_VMX;
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/*mask vmx to guest os */
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*ecx &= ~CPUID_ECX_VMX;
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/*no xsave support for guest if it is not enabled on host*/
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if ((*ecx & CPUID_ECX_OSXSAVE) == 0U) {
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*ecx &= ~CPUID_ECX_XSAVE;
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}
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*ecx &= ~CPUID_ECX_OSXSAVE;
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if ((*ecx & CPUID_ECX_XSAVE) != 0U) {
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uint64_t cr4;
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/*read guest CR4*/
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cr4 = exec_vmread(VMX_GUEST_CR4);
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if ((cr4 & CR4_OSXSAVE) != 0UL) {
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*ecx |= CPUID_ECX_OSXSAVE;
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/*no xsave support for guest if it is not enabled on host*/
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if ((*ecx & CPUID_ECX_OSXSAVE) == 0U) {
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*ecx &= ~CPUID_ECX_XSAVE;
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}
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}
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break;
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}
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case 0x0bU:
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/* Patching X2APIC */
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#ifdef CONFIG_PARTITION_MODE
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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#else
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if (is_vm0(vcpu->vm)) {
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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} else {
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*ecx = subleaf & 0xFFU;
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*edx = vlapic_get_apicid(vcpu_vlapic(vcpu));
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/* No HT emulation for UOS */
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switch (subleaf) {
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case 0U:
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*eax = 0U;
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*ebx = 1U;
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*ecx |= (1U << 8U);
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break;
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case 1U:
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if (vcpu->vm->hw.created_vcpus == 1U) {
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*eax = 0U;
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} else {
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*eax = (uint32_t)fls32(vcpu->vm->hw.created_vcpus - 1U) + 1U;
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*ecx &= ~CPUID_ECX_OSXSAVE;
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if ((*ecx & CPUID_ECX_XSAVE) != 0U) {
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uint64_t cr4;
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/*read guest CR4*/
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cr4 = exec_vmread(VMX_GUEST_CR4);
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if ((cr4 & CR4_OSXSAVE) != 0UL) {
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*ecx |= CPUID_ECX_OSXSAVE;
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}
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*ebx = vcpu->vm->hw.created_vcpus;
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*ecx |= (2U << 8U);
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}
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break;
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default:
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}
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case 0x0bU:
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/* Patching X2APIC */
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#ifdef CONFIG_PARTITION_MODE
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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#else
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if (is_vm0(vcpu->vm)) {
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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} else {
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*ecx = subleaf & 0xFFU;
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*edx = vlapic_get_apicid(vcpu_vlapic(vcpu));
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/* No HT emulation for UOS */
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switch (subleaf) {
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case 0U:
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*eax = 0U;
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*ebx = 1U;
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*ecx |= (1U << 8U);
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break;
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case 1U:
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if (vcpu->vm->hw.created_vcpus == 1U) {
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*eax = 0U;
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} else {
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*eax = (uint32_t)fls32(vcpu->vm->hw.created_vcpus - 1U) + 1U;
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}
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*ebx = vcpu->vm->hw.created_vcpus;
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*ecx |= (2U << 8U);
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break;
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default:
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*eax = 0U;
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*ebx = 0U;
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*ecx |= (0U << 8U);
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break;
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}
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}
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#endif
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break;
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case 0x0dU:
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if (!cpu_has_cap(X86_FEATURE_OSXSAVE)) {
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*eax = 0U;
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*ebx = 0U;
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*ecx |= (0U << 8U);
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break;
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*ecx = 0U;
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*edx = 0U;
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} else {
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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}
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}
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#endif
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break;
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break;
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case 0x0dU:
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if (!cpu_has_cap(X86_FEATURE_OSXSAVE)) {
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*eax = 0U;
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*ebx = 0U;
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*ecx = 0U;
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*edx = 0U;
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} else {
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cpuid_subleaf(leaf, subleaf, eax, ebx, ecx, edx);
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default:
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/*
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* In this switch statement, leaf shall either be 0x01U or 0x0bU
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* or 0x0dU. All the other cases have been handled properly
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* before this switch statement.
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* Gracefully return if prior case clauses have not been met.
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*/
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break;
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}
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break;
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default:
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/*
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* In this switch statement, leaf shall either be 0x01U or 0x0bU
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* or 0x0dU. All the other cases have been handled properly
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* before this switch statement.
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* Gracefully return if prior case clauses have not been met.
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*/
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break;
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}
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}
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