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HV: treewide: fix violations of coding guideline C-TY-02 

The coding guideline rule C-TY-02 requires that 'the operands of bit
operations shall be unsigned'. This patch adds explicit casts or literal
suffixes to make explicit the type of values involved in bit operations.
Explicit casts to widen integers before shift operations are also
introduced to make explicit that the variables are expanded BEFORE it is
shifted (which is already so in C99 but implicitly).

This patch has no semantic changes.

Tracked-On: #6776
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Junjie Mao 2021-10-29 11:34:48 +08:00 committed by wenlingz
parent b0dbc1cbfe
commit db20e277b6
4 changed files with 12 additions and 12 deletions
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8
hypervisor/acpi_parser/dmar_parse.c
View File

@ -29,8 +29,8 @@ static uint8_t get_secondary_bus(uint8_t bus, uint8_t dev, uint8_t func)
{
uint32_t data;
pio_write32(PCI_CFG_ENABLE | (bus << 16U) | (dev << 11U) |
(func << 8U) | 0x18U, PCI_CONFIG_ADDR);
pio_write32(PCI_CFG_ENABLE | ((uint32_t)bus << 16U) | ((uint32_t)dev << 11U) |
((uint32_t)func << 8U) | 0x18U, PCI_CONFIG_ADDR);
data = pio_read32(PCI_CONFIG_DATA);
@ -134,8 +134,8 @@ static int32_t handle_one_drhd(struct acpi_dmar_hardware_unit *acpi_drhd, struct
/* Disable GPU IOMMU due to gvt-d hasn’t been enabled on APL yet. */
if (is_apl_platform()) {
if (((drhd->segment << 16U) |
(dev_scope->bus << 8U) |
if ((((uint32_t)drhd->segment << 16U) |
((uint32_t)dev_scope->bus << 8U) |
dev_scope->devfun) == CONFIG_GPU_SBDF) {
drhd->ignore = true;
}

2
hypervisor/arch/x86/guest/instr_emul.c
View File

@ -1333,7 +1333,7 @@ static int32_t emulate_and(struct acrn_vcpu *vcpu, const struct instr_emul_vie *
* perform the operation with the pre-fetched immediate
* operand and write the result
*/
result = val1 & vie->immediate;
result = val1 & (uint64_t)vie->immediate;
vie_mmio_write(vcpu, result);
break;
default:

2
hypervisor/arch/x86/guest/virtual_cr.c
View File

@ -74,7 +74,7 @@ static uint64_t cr4_trap_and_passthru_mask = CR4_TRAP_AND_PASSTHRU_BITS; /* boun
#define CR4_EMRSV_BITS_PHYS_VALUE CR4_VMXE
/* The CR4 value guest expected to see for bits of CR4_EMULATED_RESERVE_BITS */
#define CR4_EMRSV_BITS_VIRT_VALUE 0
#define CR4_EMRSV_BITS_VIRT_VALUE 0UL
static uint64_t cr4_rsv_bits_guest_value;
/*

12
hypervisor/include/hw/pci.h
View File

@ -137,7 +137,7 @@
#define PCI_PTM_CAP_LEN 0x04U
#define PCIR_PTM_CAP 0x04U
#define PCIM_PTM_CAP_ROOT_CAPABLE 0x4U
#define PCIM_PTM_GRANULARITY_MASK 0xFF00
#define PCIM_PTM_GRANULARITY_MASK 0xFF00U
#define PCIR_PTM_CTRL 0x08U
#define PCIM_PTM_CTRL_ENABLED 0x1U
#define PCIM_PTM_CTRL_ROOT_SELECTED 0x2U
@ -190,11 +190,11 @@
#define PCIM_PCIE_FLR (0x1U << 15U)
/* PCI Express Device Type definitions */
#define PCIER_FLAGS 0x2
#define PCIEM_FLAGS_TYPE 0x00F0
#define PCIEM_TYPE_ENDPOINT 0x0000
#define PCIEM_TYPE_ROOTPORT 0x0004
#define PCIEM_TYPE_ROOT_INT_EP 0x0009
#define PCIER_FLAGS 0x2U
#define PCIEM_FLAGS_TYPE 0x00F0U
#define PCIEM_TYPE_ENDPOINT 0x0000U
#define PCIEM_TYPE_ROOTPORT 0x0004U
#define PCIEM_TYPE_ROOT_INT_EP 0x0009U
#define PCIR_PCIE_DEVCAP2 0x24U
#define PCIM_PCIE_DEVCAP2_ARI (0x1U << 5U)