From daf495bfc8045ab6b5fe49538376d64bc5a7ef8b Mon Sep 17 00:00:00 2001
From: Junjie Mao <junjie.mao@intel.com>
Date: Wed, 27 Jan 2021 13:02:26 +0800
Subject: [PATCH] config_tools/target: generate Software SRAM related info

This patch parsees physical RTCT entries and dump information about pseudo
RAM into the board XML files. A macro named PRE_RTVM_SW_SRAM_BASE_GPA is
added to the generated misc_cfg.h according to recent design changes.

This patch still writes the board XML file manually, following the
convention of the current framework. Using XML-based approach requires a
complete refinement of the current generation process as the root
`acrn-config` node has its own text among adjacent children.

Tracked-On: #5649
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
---
 misc/config_tools/board_config/misc_cfg_h.py | 12 ++++++
 misc/config_tools/data/tgl-rvp/tgl-rvp.xml   | 27 ++++++++++++
 misc/config_tools/target/board_parser.py     |  4 ++
 misc/config_tools/target/rtct.py             | 43 ++++++++++++++++++++
 4 files changed, 86 insertions(+)
 create mode 100644 misc/config_tools/target/rtct.py

diff --git a/misc/config_tools/board_config/misc_cfg_h.py b/misc/config_tools/board_config/misc_cfg_h.py
index 8d5a6e4af..1edb8a651 100644
--- a/misc/config_tools/board_config/misc_cfg_h.py
+++ b/misc/config_tools/board_config/misc_cfg_h.py
@@ -4,6 +4,7 @@
 #
 
 import common
+import lxml.etree
 import board_cfg_lib
 import scenario_cfg_lib
 
@@ -181,6 +182,15 @@ def pt_intx_num_vm0_gen(config):
     print("", file=config)
 
 
+def swsram_base_gpa_gen(config):
+    board_etree = lxml.etree.parse(common.BOARD_INFO_FILE)
+    bases = board_etree.xpath("//RTCT/SoftwareSRAM/base")
+    if bases:
+        min_base = min(map(lambda x: int(x.text, 16), bases))
+        print("#define PRE_RTVM_SW_SRAM_BASE_GPA\t{}UL".format(hex(min_base)), file=config)
+        print("", file=config)
+
+
 def generate_file(config):
     """
     Start to generate board.c
@@ -388,6 +398,8 @@ def generate_file(config):
 
     pt_intx_num_vm0_gen(config)
 
+    swsram_base_gpa_gen(config)
+
     print("{}".format(MISC_CFG_END), file=config)
 
     return err_dic
diff --git a/misc/config_tools/data/tgl-rvp/tgl-rvp.xml b/misc/config_tools/data/tgl-rvp/tgl-rvp.xml
index d88fe3e08..2eb667e01 100644
--- a/misc/config_tools/data/tgl-rvp/tgl-rvp.xml
+++ b/misc/config_tools/data/tgl-rvp/tgl-rvp.xml
@@ -475,4 +475,31 @@
 	16
 	</MAX_MSIX_TABLE_NUM>
 
+	<RTCT>
+		<SoftwareSRAM>
+			<cache_level>2</cache_level>
+			<base>0x40080000</base>
+			<ways>0xf0000</ways>
+			<size>0x40000</size>
+			<apic_id>0x4</apic_id>
+		</SoftwareSRAM>
+		<SoftwareSRAM>
+			<cache_level>2</cache_level>
+			<base>0x400c0000</base>
+			<ways>0xf0000</ways>
+			<size>0x40000</size>
+			<apic_id>0x6</apic_id>
+		</SoftwareSRAM>
+		<SoftwareSRAM>
+			<cache_level>3</cache_level>
+			<base>0x40080000</base>
+			<ways>0x800</ways>
+			<size>0x100000</size>
+			<apic_id>0x0</apic_id>
+			<apic_id>0x2</apic_id>
+			<apic_id>0x4</apic_id>
+			<apic_id>0x6</apic_id>
+		</SoftwareSRAM>
+	</RTCT>
+
 </acrn-config>
diff --git a/misc/config_tools/target/board_parser.py b/misc/config_tools/target/board_parser.py
index f09ff9886..1480ab51e 100755
--- a/misc/config_tools/target/board_parser.py
+++ b/misc/config_tools/target/board_parser.py
@@ -14,6 +14,7 @@ import acpi
 import clos
 import misc
 import parser_lib
+import rtct
 
 OUTPUT = "./out/"
 PY_CACHE = "__pycache__"
@@ -134,6 +135,9 @@ if __name__ == '__main__':
     # Generate misc info
     misc.generate_info(BOARD_INFO)
 
+    # Generate pseudo RAM info
+    rtct.generate_info(BOARD_INFO)
+
     with open(BOARD_INFO, 'a+') as f:
         print("</acrn-config>", file=f)
 
diff --git a/misc/config_tools/target/rtct.py b/misc/config_tools/target/rtct.py
new file mode 100644
index 000000000..c999830bc
--- /dev/null
+++ b/misc/config_tools/target/rtct.py
@@ -0,0 +1,43 @@
+# Copyright (C) 2021 Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+import os
+from acpiparser import parse_rtct
+import acpiparser.rtct
+import parser_lib
+
+def dump_psram(config):
+    print("\t<RTCT>", file=config)
+
+    rtct = None
+    if os.path.exists("/sys/firmware/acpi/tables/PTCT"):
+        rtct = parse_rtct(path="/sys/firmware/acpi/tables/PTCT")
+    elif os.path.exists("/sys/firmware/acpi/tables/RTCT"):
+        rtct = parse_rtct(path="/sys/firmware/acpi/tables/RTCT")
+
+    if rtct:
+        for entry in rtct.entries:
+            if entry.type == acpiparser.rtct.ACPI_RTCT_TYPE_SoftwareSRAM:
+                print("\t\t<SoftwareSRAM>", file=config)
+                print("\t\t\t<cache_level>{}</cache_level>".format(entry.cache_level), file=config)
+                print("\t\t\t<base>{}</base>".format(hex(entry.base)), file=config)
+                print("\t\t\t<ways>{}</ways>".format(hex(entry.ways)), file=config)
+                print("\t\t\t<size>{}</size>".format(hex(entry.size)), file=config)
+                for apic_id in entry.apic_id_tbl:
+                    print("\t\t\t<apic_id>{}</apic_id>".format(hex(apic_id)), file=config)
+                print("\t\t</SoftwareSRAM>", file=config)
+    else:
+        parser_lib.print_yel("No PTCT or RTCT found. The platform may not support pseudo RAM.")
+
+    print("\t</RTCT>", file=config)
+    print("", file=config)
+
+
+def generate_info(board_info):
+    """Get system pseudo RAM information
+    :param board_info: this is the file which stores the hardware board information
+    """
+    with open(board_info, 'a+') as config:
+        dump_psram(config)