diff --git a/devicemodel/core/sw_load_common.c b/devicemodel/core/sw_load_common.c
index 1e30712ec..abcc00663 100644
--- a/devicemodel/core/sw_load_common.c
+++ b/devicemodel/core/sw_load_common.c
@@ -54,7 +54,7 @@ static char bootargs[BOOT_ARG_LEN];
  *             Begin    Limit        Type            Length
  * 0:              0 -  0xA0000      RAM             0xA0000
  * 1:       0x100000 -  lowmem part1 RAM             0x0
- * 2:   SW SRAM_bot  -  SW SRAM_top  (reserved)      SOFTWARE_SRAM_MAX_SIZE
+ * 2:   SW SRAM_bot  -  SW SRAM_top  (reserved)      VSSRAM_MAX_SIZE
  * 3:   gpu_rsvd_bot -  gpu_rsvd_top (reserved)      0x4004000
  * 4:   lowmem part2 -  0x80000000   (reserved)      0x0
  * 5:     0xE0000000 -  0x100000000  MCFG, MMIO      512MB
@@ -76,9 +76,9 @@ const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
 	},
 
 	/*
-	 * Software SRAM area: size: 0x800000
-	 * In native, the Software SRAM region should be part of DRAM memory.
-	 * But one fixed Software SRAM gpa is friendly for virtualization due
+	 * VSSRAM area: size: 0x800000
+	 * In native, the VSSRAM region should be part of DRAM memory.
+	 * But one fixed VSSRAM gpa is friendly for virtualization due
 	 * to decoupled with various guest memory size.
 	 */
 	{
@@ -220,11 +220,11 @@ acrn_create_e820_table(struct vmctx *ctx, struct e820_entry *e820)
 {
 	uint32_t removed = 0, k;
 	uint32_t gpu_rsvmem_base_gpa = 0;
-	uint64_t software_sram_base_gpa = 0;
+	uint64_t vssram_gpa = 0;
 
 	memcpy(e820, e820_default_entries, sizeof(e820_default_entries));
 
-	/* FIXME: Here wastes 8MB memory if SSRAM is enabled, and 64MB+16KB if
+	/* FIXME: Here wastes 8MB memory if VSSRAM is enabled, and 64MB+16KB if
 	 * GPU reserved memory is exist.
 	 *
 	 * Determines the GPU region due to DSM identical mapping.
@@ -237,11 +237,11 @@ acrn_create_e820_table(struct vmctx *ctx, struct e820_entry *e820)
 		e820[LOWRAM_E820_ENTRY + 2].baseaddr = ctx->lowmem_limit;
 	}
 
-	/* Always put SW SRAM before GPU region and keep 1MB boundary for protection. */
-	software_sram_base_gpa = get_software_sram_base_gpa();
-	if (software_sram_base_gpa) {
-		e820[LOWRAM_E820_ENTRY + 1].baseaddr = software_sram_base_gpa;
-		e820[LOWRAM_E820_ENTRY + 1].length = get_software_sram_size();
+	/* Always put VSSRAM before GPU region and keep 1MB boundary for protection. */
+	vssram_gpa = get_vssram_gpa_base();
+	if (vssram_gpa) {
+		e820[LOWRAM_E820_ENTRY + 1].baseaddr = vssram_gpa;
+		e820[LOWRAM_E820_ENTRY + 1].length = get_vssram_size();
 	} else {
 		e820[LOWRAM_E820_ENTRY + 1].baseaddr = e820[LOWRAM_E820_ENTRY + 2].baseaddr;
 	}
diff --git a/devicemodel/hw/platform/acpi/acpi.c b/devicemodel/hw/platform/acpi/acpi.c
index 4ff8b2791..d1dc66949 100644
--- a/devicemodel/hw/platform/acpi/acpi.c
+++ b/devicemodel/hw/platform/acpi/acpi.c
@@ -1161,8 +1161,8 @@ int create_and_inject_vrtct(struct vmctx *ctx)
 	free(buf);
 
 	memmap.service_vm_pa = get_software_sram_base_hpa();
-	memmap.user_vm_pa = get_software_sram_base_gpa();
-	memmap.len = get_software_sram_size();
+	memmap.user_vm_pa = get_vssram_gpa_base();
+	memmap.len = get_vssram_size();
 	ioctl(ctx->fd, ACRN_IOCTL_UNSET_MEMSEG, &memmap);
 	return ioctl(ctx->fd, ACRN_IOCTL_SET_MEMSEG, &memmap);
 };
diff --git a/devicemodel/hw/platform/vssram/vssram.c b/devicemodel/hw/platform/vssram/vssram.c
index db40cf699..c119e428a 100644
--- a/devicemodel/hw/platform/vssram/vssram.c
+++ b/devicemodel/hw/platform/vssram/vssram.c
@@ -43,8 +43,8 @@ static uint32_t guest_l3_cat_shift;
 static uint32_t guest_lapicid_tbl[ACRN_PLATFORM_LAPIC_IDS_MAX];
 
 static uint64_t software_sram_base_hpa;
-static uint64_t software_sram_size;
-static uint64_t software_sram_base_gpa;
+static uint64_t vssram_size;
+static uint64_t vssram_gpa_base;
 
 static uint8_t vrtct_checksum(uint8_t *vrtct, uint32_t length)
 {
@@ -213,20 +213,20 @@ static void remap_software_sram_regions(struct acpi_table_hdr *vrtct, int rtct_v
 	}
 
 	software_sram_base_hpa = hpa_bottom;
-	software_sram_size = hpa_top - hpa_bottom;
+	vssram_size = hpa_top - hpa_bottom;
 
 	if (rtct_ver == RTCT_V1) {
 		foreach_rtct_entry(vrtct, entry) {
 			if (entry->type == RTCT_ENTRY_TYPE_SSRAM) {
 				ssram = (struct rtct_entry_data_ssram *)entry->data;
-				ssram->base = software_sram_base_gpa + (ssram->base - hpa_bottom);
+				ssram->base = vssram_gpa_base + (ssram->base - hpa_bottom);
 			}
 		}
 	} else if (rtct_ver == RTCT_V2) {
 		foreach_rtct_entry(vrtct, entry) {
 			if (entry->type == RTCT_V2_SSRAM) {
 				ssram_v2 = (struct rtct_entry_data_ssram_v2 *)entry->data;
-				ssram_v2->base = software_sram_base_gpa + (ssram_v2->base - hpa_bottom);
+				ssram_v2->base = vssram_gpa_base + (ssram_v2->base - hpa_bottom);
 			}
 		}
 	}
@@ -380,7 +380,7 @@ static int passthru_rtct_to_guest(struct acpi_table_hdr *vrtct, struct acpi_tabl
 	foreach_rtct_entry(native_rtct, entry) {
 		if (entry->type == RTCT_V2_COMPATIBILITY) {
 			compat =  (struct rtct_entry_data_compatibility *)entry->data;
-			rtct_ver = compat->RTCT_Ver_Major;
+			rtct_ver = compat->rtct_ver_major;
 			break;
 		}
 	}
@@ -425,17 +425,17 @@ uint64_t get_software_sram_base_hpa(void)
 /*
  * @pre buid_vrtct(ctx, cfg) != NULL
  */
-uint64_t get_software_sram_base_gpa(void)
+uint64_t get_vssram_gpa_base(void)
 {
-	return software_sram_base_gpa;
+	return vssram_gpa_base;
 }
 
 /*
  * @pre buid_vrtct(ctx, cfg) != NULL
  */
-uint64_t get_software_sram_size(void)
+uint64_t get_vssram_size(void)
 {
-	return software_sram_size;
+	return vssram_size;
 }
 
 /**
@@ -513,12 +513,12 @@ uint8_t *build_vrtct(struct vmctx *ctx, void *cfg)
 		guest_vcpu_num, guest_l2_cat_shift, guest_l3_cat_shift);
 
 	gpu_rsvmem_base_gpa = get_gpu_rsvmem_base_gpa();
-	software_sram_size = SOFTWARE_SRAM_MAX_SIZE;
+	vssram_size = VSSRAM_MAX_SIZE;
 	/* TODO: It is better to put one boundary between GPU region and SW SRAM
 	 * for protection.
 	 */
-	software_sram_base_gpa = ((gpu_rsvmem_base_gpa ? gpu_rsvmem_base_gpa : 0x80000000UL) -
-			software_sram_size) &  ~software_sram_size;
+	vssram_gpa_base = ((gpu_rsvmem_base_gpa ? gpu_rsvmem_base_gpa : 0x80000000UL) -
+			vssram_size) &  ~vssram_size;
 
 	if (passthru_rtct_to_guest(vrtct, rtct_cfg)) {
 		pr_err("%s, initialize vRTCT fail.", __func__);
diff --git a/devicemodel/include/pci_core.h b/devicemodel/include/pci_core.h
index f1fba5c59..5aa562c3b 100644
--- a/devicemodel/include/pci_core.h
+++ b/devicemodel/include/pci_core.h
@@ -48,8 +48,8 @@
 #define	PCI_EMUL_MEMBASE64	0x4000000000UL	/* 256GB */
 #define	PCI_EMUL_MEMLIMIT64	0x8000000000UL	/* 512GB */
 
-#define SOFTWARE_SRAM_MAX_SIZE	0x00800000UL
-#define SOFTWARE_SRAM_BASE_GPA	(PCI_EMUL_MEMBASE32 - SOFTWARE_SRAM_MAX_SIZE)
+#define VSSRAM_MAX_SIZE	0x00800000UL
+#define VSSRAM_BASE_GPA	(PCI_EMUL_MEMBASE32 - VSSRAM_MAX_SIZE)
 
 /* GVT BARs + PTDEV IO BARs */
 #define REGION_NUMS 32
@@ -297,8 +297,6 @@ void destory_io_rsvd_rgns(struct pci_vdev *vdev);
  */
 uint32_t get_gpu_rsvmem_base_gpa(void);
 uint32_t get_gpu_rsvmem_size(void);
-uint64_t get_software_sram_base_gpa(void);
-uint64_t get_software_sram_size(void);
 
 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
 			     int ioapic_irq, void *arg);
diff --git a/devicemodel/include/vssram.h b/devicemodel/include/vssram.h
index c0269d35a..c825ead24 100644
--- a/devicemodel/include/vssram.h
+++ b/devicemodel/include/vssram.h
@@ -37,10 +37,10 @@ struct rtct_entry {
 } __packed;
 
 struct rtct_entry_data_compatibility {
-	uint32_t RTCT_Ver_Major;
-	uint32_t RTCT_Ver_Minor;
-	uint32_t RTCD_Ver_Major;
-	uint32_t RTCD_Ver_Minor;
+	uint32_t rtct_ver_major;
+	uint32_t rtct_ver_minor;
+	uint32_t rtcd_ver_major;
+	uint32_t rtcd_ver_Minor;
 } __packed;
 
 struct rtct_entry_data_ssram {
@@ -65,8 +65,9 @@ struct rtct_entry_data_mem_hi_latency {
 	uint32_t apic_id_tbl[64];
 } __packed;
 
+uint64_t get_vssram_gpa_base(void);
 uint64_t get_software_sram_base_hpa(void);
-uint64_t get_software_sram_size(void);
+uint64_t get_vssram_size(void);
 uint8_t *build_vrtct(struct vmctx *ctx, void *cfg);
 
 #endif  /* RTCT_H */