From d4f789f47e4e1211d381fb835373b5002217b17b Mon Sep 17 00:00:00 2001 From: Xiaoguang Wu Date: Tue, 14 Apr 2020 11:20:36 +0800 Subject: [PATCH] hv: iommu: remove snoop related code ACRN disables Snoop Control in VT-d DMAR engines for simplifing the implementation. Also, since the snoop behavior of PCIE transactions can be controlled by guest drivers, some devices may take the advantage of the NO_SNOOP_ATTRIBUTE of PCIE transactions for better performance when snoop is not needed. No matter ACRN enables or disables Snoop Control, the DMA operations of passthrough devices behave correctly from guests' point of view. This patch is used to clean all the snoop related code. Tracked-On: #4509 Signed-off-by: Xiaoguang Wu Reviewed-by: Binbin Wu Acked-by: Eddie Dong --- hypervisor/arch/x86/guest/virtual_cr.c | 4 +--- hypervisor/arch/x86/vtd.c | 30 ++------------------------ hypervisor/include/arch/x86/pgtable.h | 2 -- hypervisor/include/arch/x86/vtd.h | 14 +----------- 4 files changed, 4 insertions(+), 46 deletions(-) diff --git a/hypervisor/arch/x86/guest/virtual_cr.c b/hypervisor/arch/x86/guest/virtual_cr.c index c2e9f853a..2fbf9bcfc 100644 --- a/hypervisor/arch/x86/guest/virtual_cr.c +++ b/hypervisor/arch/x86/guest/virtual_cr.c @@ -215,9 +215,7 @@ static void vmx_write_cr0(struct acrn_vcpu *vcpu, uint64_t cr0) * disabled behavior */ exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, PAT_ALL_UC_VALUE); - if (!iommu_snoop_supported(vcpu->vm->iommu)) { - cache_flush_invalidate_all(); - } + cache_flush_invalidate_all(); } else { /* Restore IA32_PAT to enable cache again */ exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, diff --git a/hypervisor/arch/x86/vtd.c b/hypervisor/arch/x86/vtd.c index bd3f6652b..cf784c38a 100644 --- a/hypervisor/arch/x86/vtd.c +++ b/hypervisor/arch/x86/vtd.c @@ -180,19 +180,6 @@ static inline void *get_ir_table(uint32_t dmar_index) return (void *)ir_tables[dmar_index].tables[0].contents; } -bool iommu_snoop_supported(const struct iommu_domain *iommu) -{ - bool ret; - - if ((iommu == NULL) || (iommu->iommu_snoop)) { - ret = true; - } else { - ret = false; - } - - return ret; -} - static struct dmar_drhd_rt dmar_drhd_units[MAX_DRHDS]; static bool iommu_page_walk_coherent = true; static struct dmar_info *platform_dmar_info = NULL; @@ -1024,7 +1011,7 @@ static void resume_dmar(struct dmar_drhd_rt *dmar_unit) dmar_enable_intr_remapping(dmar_unit); } -static int32_t iommu_attach_device(struct iommu_domain *domain, uint8_t bus, uint8_t devfun) +static int32_t iommu_attach_device(const struct iommu_domain *domain, uint8_t bus, uint8_t devfun) { struct dmar_drhd_rt *dmar_unit; struct dmar_entry *root_table; @@ -1052,8 +1039,6 @@ static int32_t iommu_attach_device(struct iommu_domain *domain, uint8_t bus, uin ret = -EINVAL; } else { if (iommu_ecap_sc(dmar_unit->ecap) == 0U) { - /* TODO: remove iommu_snoop from iommu_domain */ - domain->iommu_snoop = false; dev_dbg(DBG_LEVEL_IOMMU, "vm=%d add %x:%x no snoop control!", domain->vm_id, bus, devfun); } @@ -1221,17 +1206,6 @@ struct iommu_domain *create_iommu_domain(uint16_t vm_id, uint64_t translation_ta domain->trans_table_ptr = translation_table; domain->addr_width = addr_width; -#ifdef CONFIG_IOMMU_ENFORCE_SNP - domain->iommu_snoop = true; -#else - /* TODO: GPU IOMMU doesn't have snoop control capbility, - * so set domain->iommu_snoop false to enable gvt-d by default. - * If want to refine iommu snoop control policy, - * need to change domain->iommu_snoop dynamically. - */ - domain->iommu_snoop = false; -#endif - dev_dbg(DBG_LEVEL_IOMMU, "create domain [%d]: vm_id = %hu, ept@0x%x", vmid_to_domainid(domain->vm_id), domain->vm_id, domain->trans_table_ptr); } @@ -1252,7 +1226,7 @@ void destroy_iommu_domain(struct iommu_domain *domain) * @pre (from_domain != NULL) || (to_domain != NULL) */ -int32_t move_pt_device(const struct iommu_domain *from_domain, struct iommu_domain *to_domain, uint8_t bus, uint8_t devfun) +int32_t move_pt_device(const struct iommu_domain *from_domain, const struct iommu_domain *to_domain, uint8_t bus, uint8_t devfun) { int32_t status = 0; uint16_t bus_local = bus; diff --git a/hypervisor/include/arch/x86/pgtable.h b/hypervisor/include/arch/x86/pgtable.h index 37c9ba17a..7f19a79a4 100644 --- a/hypervisor/include/arch/x86/pgtable.h +++ b/hypervisor/include/arch/x86/pgtable.h @@ -108,8 +108,6 @@ /* End of ept_mem_type */ #define EPT_MT_MASK (7UL << EPT_MT_SHIFT) -/* VTD: Second-Level Paging Entries: Snoop Control */ -#define EPT_SNOOP_CTRL (1UL << 11U) #define EPT_VE (1UL << 63U) /* EPT leaf entry bits (bit 52 - bit 63) should be maksed when calculate PFN */ #define EPT_PFN_HIGH_MASK 0xFFF0000000000000UL diff --git a/hypervisor/include/arch/x86/vtd.h b/hypervisor/include/arch/x86/vtd.h index be254fe94..73690d11a 100644 --- a/hypervisor/include/arch/x86/vtd.h +++ b/hypervisor/include/arch/x86/vtd.h @@ -56,7 +56,6 @@ struct iommu_domain { uint16_t vm_id; uint32_t addr_width; /* address width of the domain */ uint64_t trans_table_ptr; - bool iommu_snoop; }; union source { @@ -605,7 +604,7 @@ struct iommu_domain; * @pre domain != NULL * */ -int32_t move_pt_device(const struct iommu_domain *from_domain, struct iommu_domain *to_domain, uint8_t bus, uint8_t devfun); +int32_t move_pt_device(const struct iommu_domain *from_domain, const struct iommu_domain *to_domain, uint8_t bus, uint8_t devfun); /** * @brief Create a iommu domain for a VM specified by vm_id. @@ -676,17 +675,6 @@ void resume_iommu(void); */ int32_t init_iommu(void); -/** - * @brief check the iommu if support cache snoop. - * - * @param[in] iommu pointer to iommu domain to check - * - * @retval true support - * @retval false not support - * - */ -bool iommu_snoop_supported(const struct iommu_domain *iommu); - /** * @brief Assign RTE for Interrupt Remapping Table. *