hv: update virtual interrupts HLD
Signed-off-by: Yan, Like <like.yan@intel.com>
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@ -11,13 +11,16 @@ management, which includes:
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- physical-to-virtual interrupt mapping for a pass-thru device, and
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- the process of VMX interrupt/exception injection.
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A guest VM never owns any physical interrupts. All interrupts received by
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A standard VM never owns any physical interrupts, all interrupts received by
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Guest OS come from a virtual interrupt injected by vLAPIC, vIOAPIC or
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vPIC. Such virtual interrupts are triggered either from a pass-through
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device or from I/O mediators in SOS via hypercalls. The
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:ref:`interrupt-remapping` section discusses how the hypervisor manages
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the mapping between physical and virtual interrupts for pass-through
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devices.
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devices. However, a hard RT VM with LAPIC pass-through does own the physical
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maskable external interrupts. On its physical CPUs, interrupts are disabled
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in VMX root mode, while in VMX non-root mode, physical interrupts will be
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deliverd to RT VM directly.
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Emulation for devices is inside SOS user space device model, i.e.,
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acrn-dm. However for performance consideration: vLAPIC, vIOAPIC, and vPIC
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@ -46,6 +49,8 @@ physical vector 0xF0 is used to kick VCPU out of its VMX non-root mode,
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used to make a request for virtual interrupt injection or other
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requests such as flush EPT.
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.. note:: the IPI based vCPU request mechanism doesn't work for the hard RT VM.
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The eventid supported for virtual interrupt injection includes:
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.. doxygengroup:: virt_int_injection
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@ -60,8 +65,8 @@ VM-Exit. For some cases there is no need to send IPI when making a request,
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because the CPU making the request itself is the target VCPU. For
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example, the #GP exception request always happens on the current CPU when it
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finds an invalid emulation has happened. An external interrupt for a pass-thru
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device always happens on the VCPUs this device belonging to, so after it
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triggers an external-interrupt VM-Exit, the current CPU is also the
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device always happens on the VCPUs of the VM which this device is belonged to,
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so after it triggers an external-interrupt VM-Exit, the current CPU is the very
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target VCPU.
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Virtual LAPIC
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@ -85,14 +90,20 @@ vLAPIC provides the same features as the native LAPIC:
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vLAPIC APIs
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===========
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APIs are provided when an interrupt source from vLAPIC needs to inject
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APIs are invoked when an interrupt source from vLAPIC needs to inject
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an interrupt, for example:
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- from LVT like LAPIC timer
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- from vIOAPIC for a pass-thru device interrupt
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- from an emulated device for a MSI
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These APIs will finish by making a request for *ACRN_REQUEST_EVENT.*
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These APIs will finish by making a vCPU request.
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_
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.. doxygenfunction:: vlapic_inject_intr
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:project: Project ACRN
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.. doxygenfunction:: vlapic_set_intr
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:project: Project ACRN
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.. doxygenfunction:: vlapic_set_local_intr
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:project: Project ACRN
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@ -100,7 +111,7 @@ These APIs will finish by making a request for *ACRN_REQUEST_EVENT.*
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.. doxygenfunction:: vlapic_intr_msi
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:project: Project ACRN
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.. doxygenfunction:: apicv_get_pir_desc_paddr
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.. doxygenfunction:: vlapic_receive_intr
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:project: Project ACRN
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EOI processing
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@ -113,24 +124,27 @@ case of EOI.
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In case of no APICv virtual interrupt delivery support, vLAPIC requires
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EOI from Guest OS whenever a vector was acknowledged and processed by
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guest. vLAPIC behavior is the same as HW LAPIC. Once an EOI is received,
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it clears the highest priority vector in ISR and TMR, and updates PPR
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status. vLAPIC will then notify vIOAPIC if the corresponding vector
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comes from vIOAPIC. This only occurs for the level triggered interrupts.
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it clears the highest priority vector in ISR, and updates PPR
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status. vLAPIC will send an EOI message to vIOAPIC if the TMR bit is set to
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indicate that is a level triggered interrupt.
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.. _lapic_passthru:
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LAPIC passthrough based on vLAPIC
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=================================
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LAPIC passthrough is supported based on vLAPIC, after switch to x2APIC
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mode. In case of LAPIC passthrough based on vLAPIC, the system will have the
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LAPIC passthrough is supported based on vLAPIC, guest OS firstly boots with
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vLAPIC in xAPIC mode and then switches to x2APIC mode to enable the LAPIC
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pass-through.
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In case of LAPIC passthrough based on vLAPIC, the system will have the
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following characteristics.
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* IRQs received by the LAPIC can be handled by the Guest VM without ``vmexit``
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* Guest VM always see virtual LAPIC IDs for security reasons
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* Guest VM always see virtual LAPIC IDs for security consideration
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* most MSRs are directly accessible from Guest VM except for ``XAPICID``,
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``LDR`` and ``ICR``. Write operations to ``ICR`` will be trapped to avoid
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malicious IPI. Read operations to ``XAPIC`` and ``LDR`` will be trapped in
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malicious IPIs. Read operations to ``XAPIC`` and ``LDR`` will be trapped in
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order to make the Guest VM always see the virtual LAPIC IDs instead of the
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physical ones.
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@ -139,7 +153,7 @@ Virtual IOAPIC
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vIOAPIC is emulated by HV when Guest accesses MMIO GPA range:
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0xFEC00000-0xFEC01000. vIOAPIC for SOS should match to the native HW
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IOAPIC Pin numbers. vIOAPIC for UOS provides 48 Pins. As the vIOAPIC is
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IOAPIC Pin numbers. vIOAPIC for guest VM provides 48 pins. As the vIOAPIC is
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always associated with vLAPIC, the virtual interrupt injection from
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vIOAPIC will finally trigger a request for vLAPIC event by calling
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vLAPIC APIs.
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@ -155,8 +169,8 @@ vLAPIC APIs.
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Virtual PIC
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***********
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vPIC is required for TSC calculation. Normally UOS will boot with
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vIOAPIC and vPIC as the source of external interrupts to Guest. On every
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vPIC is required for TSC calculation. Normally guest OS will boot with
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vIOAPIC and vPIC as the source of external interrupts. On every
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VM Exit, HV will check if there are any pending external PIC interrupts.
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vPIC APIs usage are similar to vIOAPIC.
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@ -188,20 +202,14 @@ hypervisor, for example:
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- if guest accesses an invalid vMSR register,
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- hypervisor needs to inject a #GP, or
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- during instruction emulation, an instruction fetch may access
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a non-exist page from rip_gva, at that time a #PF need be injected.
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- hypervisor needs to inject #PF when an instruction accesses a non-exist page
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from rip_gva during instruction emulation.
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ACRN hypervisor implements virtual exception injection using these APIs:
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.. doxygenfunction:: vcpu_queue_exception
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:project: Project ACRN
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.. doxygenfunction:: vcpu_inject_extint
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:project: Project ACRN
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.. doxygenfunction:: vcpu_inject_nmi
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:project: Project ACRN
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.. doxygenfunction:: vcpu_inject_gp
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:project: Project ACRN
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@ -218,6 +226,15 @@ ACRN hypervisor uses the *vcpu_inject_gp/vcpu_inject_pf* functions
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to queue exception request, and follows SDM vol3 - 6.15, Table 6-5 to
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generate double fault if the condition is met.
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ACRN hypervisor could inject *extint/nmi* using the similar vcpu APIs:
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.. doxygenfunction:: vcpu_inject_extint
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:project: Project ACRN
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.. doxygenfunction:: vcpu_inject_nmi
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:project: Project ACRN
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.. _virt-interrupt-injection:
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Virtual Interrupt Injection
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@ -226,22 +243,24 @@ Virtual Interrupt Injection
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The source of virtual interrupts comes from either DM or assigned
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devices.
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- **For SOS assigned devices**: as all devices are assigned to SOS
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directly. Whenever there is a device's physical interrupt, the
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corresponding virtual interrupts are injected to SOS via
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vLAPIC/vIOAPIC. SOS does not use vPIC and does not have emulated
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devices. See :ref:`device-assignment`.
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- **For Service VM assigned devices**: as most devices are assigned to the
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Service VM directly. Whenever there is a physical interrupt from an assigned
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device, the corresponding virtual interrupt will be injected to the Service
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VM via vLAPIC/vIOAPIC. See :ref:`device-assignment`.
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- **For UOS assigned devices**: only PCI devices could be assigned to
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UOS. Virtual interrupt injection follows the same way as SOS. A
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virtual interrupt injection operation is triggered when a
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device's physical interrupt occurs.
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- **For User VM assigned devices**: only PCI devices could be assigned to
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Uer VM. For the standard VM and soft RT VM, the virtual interrupt
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injection follows the same way as Servic VM. A virtual interrupt injection
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operation is triggered when a device's physical interrupt occurs. For the
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hard RT VM, the physical interrupts are delieverd to VM directly without
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causing VM-exit.
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- **For UOS emulated devices**: DM (acrn-dm) is responsible for UOS
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- **For User VM emulated devices**: DM is responsible for the
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emulated devices' interrupt lifecycle management. DM knows when
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an emulated device needs to assert a virtual IOPAIC/PIC Pin or
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needs to send a virtual MSI vector to Guest. These logic is
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entirely handled by DM.
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entirely handled by DM. For the hard RT VM, there should be no
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emulated devices.
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.. figure:: images/virtint-image64.png
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:align: center
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@ -255,9 +274,9 @@ that Guest ``RFLAGS.IF`` gets cleared and it would not accept any further
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interrupts. HV will check for the available Guest IRQ windows before
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injection.
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NMI is unmasked interrupt and its injection is always allowed
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NMI is unmaskable interrupt and its injection is always allowed
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regardless of the guest IRQ window status. If current IRQ
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windows is not present, HV would enable
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window is not present, HV would enable
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``MSR_IA32_VMX_PROCBASED_CTLS_IRQ_WIN (PROCBASED_CTRL.bit[2])`` and
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VM Enter directly. The injection will be done on next VM Exit once Guest
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issues ``STI (GuestRFLAG.IF=1)``.
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