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HV: fix MISRA violation of cpu state table 

Per MISRA C, the dimention of a array must be specified.

Tracked-On: #3477

Signed-off-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Victor Sun 2019-07-29 09:30:27 +08:00 committed by wenlingz
parent a092f40009
commit cd3b8ed7f1
1 changed files with 8 additions and 8 deletions
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16
hypervisor/arch/x86/cpu_state_tbl.c
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@ -11,7 +11,7 @@
#include <cpu_caps.h>
/* The table includes cpu px info of Intel A3960 SoC */
static const struct cpu_px_data px_a3960[] = {
static const struct cpu_px_data px_a3960[17] = {
{0x960UL, 0UL, 0xAUL, 0xAUL, 0x1800UL, 0x1800UL}, /* P0 */
{0x8FCUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P1 */
{0x898UL, 0UL, 0xAUL, 0xAUL, 0x1600UL, 0x1600UL}, /* P2 */
@ -32,14 +32,14 @@ static const struct cpu_px_data px_a3960[] = {
};
/* The table includes cpu cx info of Intel Broxton SoC such as A39x0, J3455, N3350 */
static const struct cpu_cx_data cx_bxt[] = {
static const struct cpu_cx_data cx_bxt[3] = {
{{SPACE_FFixedHW, 0x0U, 0U, 0U, 0UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */
{{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x415UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */
{{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x419UL}, 0x3U, 0x96U, 0x0AUL} /* C3 */
};
/* The table includes cpu px info of Intel A3950 SoC */
static const struct cpu_px_data px_a3950[] = {
static const struct cpu_px_data px_a3950[13] = {
{0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P0 */
{0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P1 */
{0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P2 */
@ -56,7 +56,7 @@ static const struct cpu_px_data px_a3950[] = {
};
/* The table includes cpu px info of Intel J3455 SoC */
static const struct cpu_px_data px_j3455[] = {
static const struct cpu_px_data px_j3455[9] = {
{0x5DDUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P0 */
{0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P1 */
{0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P2 */
@ -69,7 +69,7 @@ static const struct cpu_px_data px_j3455[] = {
};
/* The table includes cpu px info of Intel N3350 SoC */
static const struct cpu_px_data px_n3350[] = {
static const struct cpu_px_data px_n3350[5] = {
{0x44DUL, 0UL, 0xAUL, 0xAUL, 0x1800UL, 0x1800UL}, /* P0 */
{0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P1 */
{0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P2 */
@ -78,7 +78,7 @@ static const struct cpu_px_data px_n3350[] = {
};
/* The table includes cpu cx info of Intel i7-8650U SoC */
static const struct cpu_px_data px_i78650[] = {
static const struct cpu_px_data px_i78650[16] = {
{0x835UL, 0x0UL, 0xAUL, 0xAUL, 0x2A00UL, 0x2A00UL}, /* P0 */
{0x834UL, 0x0UL, 0xAUL, 0xAUL, 0x1500UL, 0x1500UL}, /* P1 */
{0x76CUL, 0x0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P2 */
@ -98,7 +98,7 @@ static const struct cpu_px_data px_i78650[] = {
};
/* The table includes cpu cx info of Intel i7-8650U SoC */
static const struct cpu_cx_data cx_i78650[] = {
static const struct cpu_cx_data cx_i78650[3] = {
{{SPACE_FFixedHW, 0x0U, 0U, 0U, 0UL}, 0x1U, 0x1U, 0UL}, /* C1 */
{{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x1816UL}, 0x2U, 0x97U, 0UL}, /* C2 */
{{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x1819UL}, 0x3U, 0x40AU, 0UL} /* C3 */
@ -107,7 +107,7 @@ static const struct cpu_cx_data cx_i78650[] = {
static const struct cpu_state_table {
char model_name[64];
struct cpu_state_info state_info;
} cpu_state_tbl[] = {
} cpu_state_tbl[5] = {
{"Intel(R) Atom(TM) Processor A3960 @ 1.90GHz",
{(uint8_t)ARRAY_SIZE(px_a3960), px_a3960,
(uint8_t)ARRAY_SIZE(cx_bxt), cx_bxt}