diff --git a/misc/acrn-config/library/scenario_cfg_lib.py b/misc/acrn-config/library/scenario_cfg_lib.py
index 9ba6ca208..5cec359a2 100644
--- a/misc/acrn-config/library/scenario_cfg_lib.py
+++ b/misc/acrn-config/library/scenario_cfg_lib.py
@@ -588,6 +588,10 @@ def check_vuart(v0_vuart, v1_vuart):
 
 
 def vcpu_clos_check(cpus_per_vm, clos_per_vm, prime_item, item):
+
+    if not board_cfg_lib.is_rdt_supported():
+        return
+
     common_clos_max = 0
     cdp_enabled = cdp_enabled = common.get_hv_item_tag(common.SCENARIO_INFO_FILE, "FEATURES", "RDT", "CDP_ENABLED")
     (rdt_resources, rdt_res_clos_max, _) = board_cfg_lib.clos_info_parser(common.BOARD_INFO_FILE)
diff --git a/misc/acrn-config/xmls/config-xmls/whl-ipc-i7/industry.xml b/misc/acrn-config/xmls/config-xmls/whl-ipc-i7/industry.xml
index f1fe9985c..5a0e4dfed 100644
--- a/misc/acrn-config/xmls/config-xmls/whl-ipc-i7/industry.xml
+++ b/misc/acrn-config/xmls/config-xmls/whl-ipc-i7/industry.xml
@@ -136,6 +136,7 @@
     </cpu_affinity>
     <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
         <vcpu_clos>0</vcpu_clos>
+        <vcpu_clos>0</vcpu_clos>
     </clos>
     <epc_section configurable="0" desc="epc section">
         <base desc="SGX EPC section base, must be page aligned">0</base>