Introduce ACRN Inter-VM Virtualization
Support shared memory based inter-vm communication for ACRN
post-launched VMs. The ivshmem mediator emulates one standard
PCI device which expose the shared memory region through its BAR2.
The shared memory region is allocated through Linux shm mechanism and
post-launched VM needs to specify the shm name and size as the acrn-dm
parameter, the VMs have same shm name parameter can communicate over
the shared memory.
For first stage, only support shared memory. Consider to support
notification(interrupt) in future.
To add a ivshmem device in device model, the usage as below
-s N,ivshmem,shm_name,shm_size
v2: Implement the ivshmem MMIO registers emulation
v3: Refine code style
Add ivshmem device usage
Refine MMIO register return value
v4: Refine comments
Use logger interfaces to print logs
Tracked-On: #4853
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Yuan Liu
wenlingz
parent
884e9fc911
commit
cb816f7f65
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@ -0,0 +1,198 @@
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/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* ACRN Inter-VM Virtualizaiton based on ivshmem-v1 device
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*
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* +----------+ +-----------------------------------------+ +----------+
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* |Postlaunch| | Service OS | |Postlaunch|
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* | VM | | | | VM |
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* | | | Interrupt | | |
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* |+--------+| |+----------+ Foward +----------+| |+--------+|
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* || App || || acrn-dm | +-------+ | acrn-dm || || App ||
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* || || ||+--------+| |ivshmem| |+--------+|| || ||
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* |+---+----+| |||ivshmem ||<---+server +--->||ivshmem ||| |+---+----+|
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* | | | +-+++ dm || +-------+ || dm +++-+ | | |
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* | | | | ||+---+----+| |+----+---+|| | | | |
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* |+---+----+| | |+----^-----+ +-----^----+| | |+---+----+|
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* ||UIO || | | +---------------+-------------+ | | ||UIO ||
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* ||driver || | | v | | ||driver ||
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* |+---+----+| | | +--------+-------+ | | |+---+----+|
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* | | | | | | /dev/shm | | | | | |
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* | | | | | +--------+-------+ | | | | |
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* |+---+----+| | | | | | |+---+----+|
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* ||ivshmem || | | +--------+-------+ | | ||ivshmem ||
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* ||device || | | | Shared Memory | | | ||device ||
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* |+---+----+| | | +----------------+ | | |+---+----+|
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* +----+-----+ | +-----------------------------------------+ | +----+-----+
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* +--------+ +-------+
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*
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*/
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#include <string.h>
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#include <unistd.h>
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#include <stdio.h>
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#include <sys/mman.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <errno.h>
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#include <stdlib.h>
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#include "pci_core.h"
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#include "vmmapi.h"
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#include "dm_string.h"
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#include "log.h"
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#define IVSHMEM_MMIO_BAR 0
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#define IVSHMEM_MEM_BAR 2
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#define IVSHMEM_VENDOR_ID 0x1af4
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#define IVSHMEM_DEVICE_ID 0x1110
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#define IVSHMEM_CLASS 0x05
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#define IVSHMEM_REV 0x01
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/* IVSHMEM MMIO Registers */
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#define IVSHMEM_REG_SIZE 0x100
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#define IVSHMEM_IRQ_MASK_REG 0x00
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#define IVSHMEM_IRQ_STA_REG 0x04
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#define IVSHMEM_IV_POS_REG 0x08
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#define IVSHMEM_DOORBELL_REG 0x0c
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#define IVSHMEM_RESERVED_REG 0x0f
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static void
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pci_ivshmem_write(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
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int baridx, uint64_t offset, int size, uint64_t value)
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{
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pr_dbg("%s: baridx %d, offset = %lx, value = 0x%lx\n",
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__func__, baridx, offset, value);
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if (baridx == IVSHMEM_MMIO_BAR) {
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switch (offset) {
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/*
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* Following registers are used to support
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* notification/interrupt in future.
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*/
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case IVSHMEM_IRQ_MASK_REG:
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case IVSHMEM_IRQ_STA_REG:
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break;
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case IVSHMEM_DOORBELL_REG:
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pr_warn("Doorbell capability doesn't support for now, ignore vectors 0x%lx, peer id %lu\n",
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value & 0xff, ((value >> 16) & 0xff));
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break;
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default:
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pr_dbg("%s: invalid device register 0x%lx\n",
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__func__, offset);
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break;
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}
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}
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}
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uint64_t
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pci_ivshmem_read(struct vmctx *ctx, int vcpu, struct pci_vdev *dev,
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int baridx, uint64_t offset, int size)
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{
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uint64_t val = ~0;
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pr_dbg("%s: baridx %d, offset = 0x%lx, size = 0x%x\n",
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__func__, baridx, offset, size);
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if (baridx == IVSHMEM_MMIO_BAR) {
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switch (offset) {
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/*
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* Following registers are used to support
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* notification/interrupt in future.
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*/
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case IVSHMEM_IRQ_MASK_REG:
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case IVSHMEM_IRQ_STA_REG:
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val = 0;
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break;
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/*
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* If ivshmem device doesn't support interrupt,
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* The IVPosition is zero. otherwise, it is Peer ID.
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*/
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case IVSHMEM_IV_POS_REG:
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val = 0;
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break;
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default:
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pr_dbg("%s: invalid device register 0x%lx\n",
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__func__, offset);
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break;
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}
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}
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switch (size) {
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case 1:
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val &= 0xFF;
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break;
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case 2:
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val &= 0xFFFF;
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break;
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case 4:
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val &= 0xFFFFFFFF;
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break;
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}
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return val;
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}
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static int
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pci_ivshmem_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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{
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uint32_t size;
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char *tmp, *name, *orig;
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/* ivshmem device usage: "-s N,ivshmem,shm_name,shm_size" */
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tmp = orig = strdup(opts);
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if (!orig) {
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pr_warn("No memory for strdup\n");
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goto err;
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}
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name = strsep(&tmp, ",");
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if (!name) {
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pr_warn("the shared memory size is not set\n");
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goto err;
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}
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if (dm_strtoui(tmp, &tmp, 10, &size) != 0) {
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pr_warn("the shared memory size is incorrect, %s\n", tmp);
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goto err;
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}
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if (size < 4096 || size > 128 * 1024 * 1024 ||
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(size & (size - 1)) != 0) {
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pr_warn("invalid shared memory size %u, the size range is [4K,128M] bytes and value must be a power of 2\n",
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size);
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goto err;
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}
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/* initialize config space */
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pci_set_cfgdata16(dev, PCIR_VENDOR, IVSHMEM_VENDOR_ID);
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pci_set_cfgdata16(dev, PCIR_DEVICE, IVSHMEM_DEVICE_ID);
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pci_set_cfgdata16(dev, PCIR_REVID, IVSHMEM_REV);
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pci_set_cfgdata8(dev, PCIR_CLASS, IVSHMEM_CLASS);
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pci_emul_alloc_bar(dev, IVSHMEM_MMIO_BAR, PCIBAR_MEM32, IVSHMEM_REG_SIZE);
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pci_emul_alloc_bar(dev, IVSHMEM_MEM_BAR, PCIBAR_MEM64, size);
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free(orig);
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return 0;
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err:
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if (orig)
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free(orig);
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return -1;
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}
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static void
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pci_ivshmem_deinit(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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{
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}
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struct pci_vdev_ops pci_ops_ivshmem = {
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.class_name = "ivshmem",
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.vdev_init = pci_ivshmem_init,
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.vdev_deinit = pci_ivshmem_deinit,
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.vdev_barwrite = pci_ivshmem_write,
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.vdev_barread = pci_ivshmem_read
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};
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DEFINE_PCI_DEVTYPE(pci_ops_ivshmem);
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