From ca65e8c7276e1b06f777e3cef2fac1bd3ed12ea1 Mon Sep 17 00:00:00 2001 From: Victor Sun Date: Sat, 13 Oct 2018 00:12:23 +0800 Subject: [PATCH] HV: refine APIC base address to platform acpi info The base address of LAPIC and IOAPIC should be parsed from MADT table, so move the definition to platform_acpi_info.h. Tracked-On: #1500 Signed-off-by: Victor Sun Reviewed-by: Junjie Mao Acked-by: Eddie Dong --- hypervisor/arch/x86/ioapic.c | 19 ++++++------------- .../bsp/include/sbl/platform_acpi_info.h | 4 ++++ .../bsp/include/uefi/platform_acpi_info.h | 4 ++++ hypervisor/include/arch/x86/apicreg.h | 3 --- hypervisor/include/arch/x86/lapic.h | 3 --- 5 files changed, 14 insertions(+), 19 deletions(-) diff --git a/hypervisor/arch/x86/ioapic.c b/hypervisor/arch/x86/ioapic.c index d8cb07195..a6be55734 100644 --- a/hypervisor/arch/x86/ioapic.c +++ b/hypervisor/arch/x86/ioapic.c @@ -122,25 +122,18 @@ ioapic_write_reg32(const void *ioapic_base, spinlock_irqrestore_release(&ioapic_lock, rflags); } +/** + * @pre apic_id < 2 + */ static inline uint64_t get_ioapic_base(uint8_t apic_id) { - uint64_t addr = 0xffffffffffffffffUL; + const uint64_t addr[2] = {IOAPIC0_BASE, IOAPIC1_BASE}; - /* should extract next ioapic from ACPI MADT table */ - if (apic_id == 0U) { - addr = DEFAULT_IO_APIC_BASE; - } else if (apic_id == 1U) { - addr = 0xfec3f000UL; - } else if (apic_id == 2U) { - addr = 0xfec7f000UL; - } else { - ASSERT(apic_id <= 2U, "ACPI MADT table missing"); - } - return addr; + /* the ioapic base should be extracted from ACPI MADT table */ + return addr[apic_id]; } - static inline void ioapic_get_rte_entry(void *ioapic_addr, uint8_t pin, union ioapic_rte *rte) diff --git a/hypervisor/bsp/include/sbl/platform_acpi_info.h b/hypervisor/bsp/include/sbl/platform_acpi_info.h index ab3185e1f..aca02145b 100644 --- a/hypervisor/bsp/include/sbl/platform_acpi_info.h +++ b/hypervisor/bsp/include/sbl/platform_acpi_info.h @@ -13,7 +13,11 @@ #define ACPI_INFO_VALIDATED /* APIC */ +#define LAPIC_BASE 0xFEE00000UL + #define NR_IOAPICS 1U +#define IOAPIC0_BASE 0xFEC00000UL +#define IOAPIC1_BASE 0UL /* pm sstate data */ #define PM1A_EVT_SPACE_ID SPACE_SYSTEM_IO diff --git a/hypervisor/bsp/include/uefi/platform_acpi_info.h b/hypervisor/bsp/include/uefi/platform_acpi_info.h index 9ffbefa23..f1d2a0a9e 100644 --- a/hypervisor/bsp/include/uefi/platform_acpi_info.h +++ b/hypervisor/bsp/include/uefi/platform_acpi_info.h @@ -11,7 +11,11 @@ #define PLATFORM_ACPI_INFO_H /* APIC */ +#define LAPIC_BASE 0xFEE00000UL + #define NR_IOAPICS 1U +#define IOAPIC0_BASE 0xFEC00000UL +#define IOAPIC1_BASE 0UL /* pm sstate data */ #define PM1A_EVT_SPACE_ID SPACE_SYSTEM_IO diff --git a/hypervisor/include/arch/x86/apicreg.h b/hypervisor/include/arch/x86/apicreg.h index 2caee61d7..4930b24fa 100644 --- a/hypervisor/include/arch/x86/apicreg.h +++ b/hypervisor/include/arch/x86/apicreg.h @@ -350,9 +350,6 @@ union ioapic_rte { * I/O APIC defines */ -/* default physical locations of an IO APIC */ -#define DEFAULT_IO_APIC_BASE 0xfec00000UL - /* window register offset */ #define IOAPIC_REGSEL 0x00U #define IOAPIC_WINDOW 0x10U diff --git a/hypervisor/include/arch/x86/lapic.h b/hypervisor/include/arch/x86/lapic.h index a6de8d908..a0b303769 100644 --- a/hypervisor/include/arch/x86/lapic.h +++ b/hypervisor/include/arch/x86/lapic.h @@ -33,9 +33,6 @@ #define INTR_LAPIC_ICR_ALL_INC_SELF 0x2U #define INTR_LAPIC_ICR_ALL_EX_SELF 0x3U -/* Default LAPIC base */ -#define LAPIC_BASE 0xFEE00000U - /* LAPIC register bit and bitmask definitions */ #define LAPIC_SVR_VECTOR 0x000000FFU #define LAPIC_SVR_APIC_ENABLE_MASK 0x00000100U