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fix spec_ctrl msr save/restore 

the CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL is 168U which should be 0xa8
instead of 0xa0

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Jason Chen CJ 2018-08-16 14:56:25 +08:00 committed by lijinxia
parent 022ef92b62
commit c234acb338
1 changed files with 6 additions and 6 deletions
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12
hypervisor/arch/x86/vmx_asm.S
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@ -59,8 +59,8 @@ vmx_vmrun:
/* 0x00000048 = MSR_IA32_SPEC_CTRL */
movl $0x00000048,%ecx
/*0xa0=168U=CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL*/
mov 0xa0(%rdi),%rax
/*0xa8=168U=CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL*/
mov 0xa8(%rdi),%rax
movl $0,%edx
wrmsr
@ -231,8 +231,8 @@ vm_eval_error:
*/
movl $0x00000048,%ecx
rdmsr
/*168U=0xa0=CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL*/
mov %rax,0xa0(%rsi)
/*168U=0xa8=CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL*/
mov %rax,0xa8(%rsi)
/* 0x1 = SPEC_ENABLE_IBRS */
movl $0x1,%eax
movl $0,%edx
@ -255,8 +255,8 @@ ibrs_opt:
*/
movl $0x00000048,%ecx
rdmsr
/*168U=0xa0=CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL*/
mov %rax,0xa0(%rsi)
/*168U=0xa8=CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL*/
mov %rax,0xa8(%rsi)
/* 0x2 = SPEC_ENABLE_STIBP */
movl $0x2,%eax
movl $0,%edx