HV:vtd:fix all integer related violations
Fix vtd.h and vtd.c all integer violations. Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Huihuang Shi
lijinxia
parent
4c941ed47b
commit
c0b55cdf1b
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@ -14,13 +14,13 @@
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#define ACRN_DBG_IOMMU LOG_INFO
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#define DMAR_FAULT_LOOP_MAX 10
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#else
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#define ACRN_DBG_IOMMU 6
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#define ACRN_DBG_IOMMU 6U
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#endif
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/* set an appropriate bus limitation when iommu init,
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* to reduce memory & time cost
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*/
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#define IOMMU_INIT_BUS_LIMIT (0xf)
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#define IOMMU_INIT_BUS_LIMIT (0xfU)
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#define PAGE_MASK (0xFFFUL)
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#define LEVEL_WIDTH 9U
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@ -124,7 +124,7 @@ struct dmar_drhd_rt {
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uint64_t cap;
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uint64_t ecap;
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uint64_t gcmd; /* sw cache value of global cmd register */
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uint32_t gcmd; /* sw cache value of global cmd register */
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uint32_t irq;
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struct dev_handler_node *dmar_irq_node;
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@ -166,7 +166,7 @@ static uint32_t dmar_hdrh_unit_count;
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* domain id 0 is reserved,
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* bit0 --> domain id 0, ..., bit63 --> domain id 63
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*/
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static uint32_t max_domain_id = 63;
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static uint32_t max_domain_id = 63U;
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static uint64_t domain_bitmap;
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static spinlock_t domain_lock;
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static struct iommu_domain *host_domain;
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@ -182,7 +182,7 @@ static void register_hrhd_units(void)
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uint32_t i;
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for (i = 0U; i < info->drhd_count; i++) {
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drhd_rt = calloc(1, sizeof(struct dmar_drhd_rt));
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drhd_rt = calloc(1U, sizeof(struct dmar_drhd_rt));
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ASSERT(drhd_rt != NULL, "");
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drhd_rt->drhd = &info->drhd_units[i];
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dmar_register_hrhd(drhd_rt);
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@ -198,8 +198,8 @@ static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
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{
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uint64_t value;
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value = mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4));
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value = value << 32;
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value = mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
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value = value << 32U;
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value = value | mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr +
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offset));
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@ -217,11 +217,11 @@ static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
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{
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uint32_t temp;
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temp = value;
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temp = (uint32_t)value;
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mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
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temp = value >> 32;
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mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4));
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temp = (uint32_t)(value >> 32U);
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mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4U));
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}
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/* flush cache when root table, context table updated */
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@ -313,7 +313,7 @@ static void dmar_uint_show_capability(struct dmar_drhd_rt *dmar_uint)
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static inline uint8_t width_to_level(uint32_t width)
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{
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return ((width - 12U) + (LEVEL_WIDTH)-1U) / (LEVEL_WIDTH);
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return (uint8_t)(((width - 12U) + (LEVEL_WIDTH)-1U) / (LEVEL_WIDTH));
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}
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static inline uint8_t width_to_agaw(uint32_t width)
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@ -387,7 +387,7 @@ static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint)
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dmar_uint->cap = iommu_read64(dmar_uint, DMAR_CAP_REG);
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dmar_uint->ecap = iommu_read64(dmar_uint, DMAR_ECAP_REG);
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dmar_uint->gcmd = iommu_read64(dmar_uint, DMAR_GCMD_REG);
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dmar_uint->gcmd = iommu_read32(dmar_uint, DMAR_GCMD_REG);
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dmar_uint->cap_msagaw = dmar_uint_get_msagw(dmar_uint);
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@ -395,7 +395,7 @@ static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint)
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iommu_cap_num_fault_regs(dmar_uint->cap);
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dmar_uint->cap_fault_reg_offset =
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iommu_cap_fault_reg_offset(dmar_uint->cap);
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dmar_uint->ecap_iotlb_offset = iommu_ecap_iro(dmar_uint->ecap) * 16;
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dmar_uint->ecap_iotlb_offset = iommu_ecap_iro(dmar_uint->ecap) * 16U;
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#if DBG_IOMMU
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pr_info("version:0x%x, cap:0x%llx, ecap:0x%llx",
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@ -411,11 +411,11 @@ static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint)
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#endif
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/* check capability */
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if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x1UL) == 0) {
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if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x1U) == 0U) {
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dev_dbg(ACRN_DBG_IOMMU, "dmar uint doesn't support 2MB page!");
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}
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if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x2UL) == 0) {
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if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x2U) == 0U) {
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dev_dbg(ACRN_DBG_IOMMU, "dmar uint doesn't support 1GB page!");
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}
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@ -450,7 +450,7 @@ static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint)
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dmar_hdrh_unit_count++;
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if ((dmar_uint->gcmd & DMA_GCMD_TE) != 0) {
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if ((dmar_uint->gcmd & DMA_GCMD_TE) != 0U) {
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dmar_disable_translation(dmar_uint);
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}
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}
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@ -498,7 +498,7 @@ static uint8_t alloc_domain_id(void)
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*/
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for (i = 1U; i < 64U; i++) {
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mask = (1UL << i);
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if ((domain_bitmap & mask) == 0) {
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if ((domain_bitmap & mask) == 0UL) {
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domain_bitmap |= mask;
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break;
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}
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@ -518,7 +518,7 @@ static void free_domain_id(uint16_t dom_id)
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static struct iommu_domain *create_host_domain(void)
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{
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struct iommu_domain *domain = calloc(1, sizeof(struct iommu_domain));
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struct iommu_domain *domain = calloc(1U, sizeof(struct iommu_domain));
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ASSERT(domain != NULL, "");
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domain->is_host = true;
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@ -539,7 +539,7 @@ static void dmar_write_buffer_flush(struct dmar_drhd_rt *dmar_uint)
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}
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IOMMU_LOCK(dmar_uint);
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iommu_write64(dmar_uint, DMAR_GCMD_REG,
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iommu_write32(dmar_uint, DMAR_GCMD_REG,
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dmar_uint->gcmd | DMA_GCMD_WBF);
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/* read lower 32 bits to check */
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@ -589,7 +589,7 @@ static void dmar_invalid_context_cache(struct dmar_drhd_rt *dmar_uint,
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static void dmar_invalid_context_cache_global(struct dmar_drhd_rt *dmar_uint)
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{
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dmar_invalid_context_cache(dmar_uint, 0, 0, 0, DMAR_CIRG_GLOBAL);
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dmar_invalid_context_cache(dmar_uint, 0U, 0U, 0U, DMAR_CIRG_GLOBAL);
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}
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static void dmar_invalid_iotlb(struct dmar_drhd_rt *dmar_uint,
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@ -600,7 +600,7 @@ static void dmar_invalid_iotlb(struct dmar_drhd_rt *dmar_uint,
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* if hardware doesn't support it, will be ignored by hardware
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*/
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uint64_t cmd = DMA_IOTLB_IVT | DMA_IOTLB_DR | DMA_IOTLB_DW;
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uint64_t addr = 0;
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uint64_t addr = 0UL;
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uint32_t status;
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switch (iirg) {
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@ -626,9 +626,9 @@ static void dmar_invalid_iotlb(struct dmar_drhd_rt *dmar_uint,
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iommu_write64(dmar_uint, dmar_uint->ecap_iotlb_offset, addr);
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}
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iommu_write64(dmar_uint, dmar_uint->ecap_iotlb_offset + 8, cmd);
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iommu_write64(dmar_uint, dmar_uint->ecap_iotlb_offset + 8U, cmd);
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/* read upper 32bits to check */
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DMAR_WAIT_COMPLETION(dmar_uint->ecap_iotlb_offset + 12,
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DMAR_WAIT_COMPLETION(dmar_uint->ecap_iotlb_offset + 12U,
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(status & DMA_IOTLB_IVT_32) == 0U, status);
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IOMMU_UNLOCK(dmar_uint);
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@ -645,7 +645,7 @@ static void dmar_invalid_iotlb(struct dmar_drhd_rt *dmar_uint,
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*/
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static void dmar_invalid_iotlb_global(struct dmar_drhd_rt *dmar_uint)
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{
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dmar_invalid_iotlb(dmar_uint, 0, 0, 0, 0, DMAR_IIRG_GLOBAL);
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dmar_invalid_iotlb(dmar_uint, 0U, 0UL, 0U, false, DMAR_IIRG_GLOBAL);
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}
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static void dmar_set_root_table(struct dmar_drhd_rt *dmar_uint)
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@ -678,12 +678,12 @@ static void dmar_fault_event_mask(struct dmar_drhd_rt *dmar_uint)
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static void dmar_fault_event_unmask(struct dmar_drhd_rt *dmar_uint)
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{
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IOMMU_LOCK(dmar_uint);
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iommu_write32(dmar_uint, DMAR_FECTL_REG, 0);
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iommu_write32(dmar_uint, DMAR_FECTL_REG, 0U);
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IOMMU_UNLOCK(dmar_uint);
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}
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static void dmar_fault_msi_write(struct dmar_drhd_rt *dmar_uint,
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uint8_t vector)
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uint32_t vector)
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{
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uint32_t data;
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uint32_t addr_low;
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@ -780,8 +780,8 @@ static int dmar_fault_handler(int irq, void *data)
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while (dma_fsts_ppf(fsr)) {
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loop++;
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index = dma_fsts_fri(fsr);
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record_reg_offset = dmar_uint->cap_fault_reg_offset
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+ index * 16;
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record_reg_offset = (uint32_t)dmar_uint->cap_fault_reg_offset
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+ index * 16U;
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if (index >= dmar_uint->cap_num_fault_regs) {
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dev_dbg(ACRN_DBG_IOMMU, "%s: invalid FR Index",
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__func__);
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@ -790,7 +790,7 @@ static int dmar_fault_handler(int irq, void *data)
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/* read 128-bit fault recording register */
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record[0] = iommu_read64(dmar_uint, record_reg_offset);
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record[1] = iommu_read64(dmar_uint, record_reg_offset + 8);
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record[1] = iommu_read64(dmar_uint, record_reg_offset + 8U);
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dev_dbg(ACRN_DBG_IOMMU, "%s: record[%d] @0x%x: 0x%llx, 0x%llx",
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__func__, index, record_reg_offset,
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@ -800,7 +800,7 @@ static int dmar_fault_handler(int irq, void *data)
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/* write to clear */
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iommu_write64(dmar_uint, record_reg_offset, record[0]);
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iommu_write64(dmar_uint, record_reg_offset + 8, record[1]);
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iommu_write64(dmar_uint, record_reg_offset + 8U, record[1]);
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#ifdef DMAR_FAULT_LOOP_MAX
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if (loop > DMAR_FAULT_LOOP_MAX) {
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@ -1147,8 +1147,8 @@ int assign_iommu_device(struct iommu_domain *domain, uint8_t bus,
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/* TODO: check if the device assigned */
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remove_iommu_device(host_domain, 0, bus, devfun);
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add_iommu_device(domain, 0, bus, devfun);
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remove_iommu_device(host_domain, 0U, bus, devfun);
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add_iommu_device(domain, 0U, bus, devfun);
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return 0;
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}
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@ -1161,8 +1161,8 @@ int unassign_iommu_device(struct iommu_domain *domain, uint8_t bus,
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/* TODO: check if the device assigned */
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remove_iommu_device(domain, 0, bus, devfun);
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add_iommu_device(host_domain, 0, bus, devfun);
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remove_iommu_device(domain, 0U, bus, devfun);
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add_iommu_device(host_domain, 0U, bus, devfun);
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return 0;
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}
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@ -1295,7 +1295,7 @@ void init_iommu(void)
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for (bus = 0U; bus <= IOMMU_INIT_BUS_LIMIT; bus++) {
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for (devfun = 0U; devfun <= 255U; devfun++) {
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add_iommu_device(host_domain, 0,
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add_iommu_device(host_domain, 0U,
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(uint8_t)bus, (uint8_t)devfun);
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}
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}
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@ -137,7 +137,7 @@
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#include <cpu.h>
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/* Define cache line size (in bytes) */
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#define CACHE_LINE_SIZE 64
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#define CACHE_LINE_SIZE 64U
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/* Size of all page structures for IA-32e */
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#define IA32E_STRUCT_SIZE MEM_4K
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