hv: vmtrr: hide mtrr if hide_mtrr is true
Now we only configure "hide MTRR" explicitly to false for SOS. For other VMs, we don't configure it which means hide_mtrr is false by default. And remove global config MTRR_ENABLED Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com>
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@ -274,10 +274,6 @@ config GPU_SBDF
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00:02.0 in DRHD segment 0, this SBDF would be (0 << 16) | (0 << 8) |
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(2 << 3) | (0 << 0), i.e. 0x00000010.
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config MTRR_ENABLED
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bool "Memory Type Range Registers (MTRR) enabled"
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default y
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config RELOC
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bool "Enable hypervisor relocation"
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default y
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@ -391,9 +391,9 @@ int32_t create_vcpu(uint16_t pcpu_id, struct acrn_vm *vm, struct acrn_vcpu **rtn
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/* Create per vcpu vlapic */
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vlapic_create(vcpu);
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#ifdef CONFIG_MTRR_ENABLED
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init_vmtrr(vcpu);
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#endif
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if (!vm_hide_mtrr(vm)) {
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init_vmtrr(vcpu);
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}
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spinlock_init(&(vcpu->arch.lock));
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@ -322,10 +322,10 @@ void guest_cpuid(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t
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*ebx &= ~APIC_ID_MASK;
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*ebx |= (apicid << APIC_ID_SHIFT);
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#ifndef CONFIG_MTRR_ENABLED
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/* mask mtrr */
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*edx &= ~CPUID_EDX_MTRR;
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#endif
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if (vm_hide_mtrr(vcpu->vm)) {
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/* mask mtrr */
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*edx &= ~CPUID_EDX_MTRR;
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}
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/* mask Debug Store feature */
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*ecx &= ~(CPUID_ECX_DTES64 | CPUID_ECX_DS_CPL);
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@ -71,6 +71,16 @@ bool is_lapic_pt(const struct acrn_vm *vm)
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return ((vm_config->guest_flags & LAPIC_PASSTHROUGH) != 0U);
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}
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/**
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* @pre vm != NULL && vm_config != NULL && vm->vmid < CONFIG_MAX_VM_NUM
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*/
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bool vm_hide_mtrr(const struct acrn_vm *vm)
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{
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struct acrn_vm_config *vm_config = get_vm_config(vm->vm_id);
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return ((vm_config->guest_flags & HIDE_MTRR) != 0U);
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}
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/**
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* @brief Initialize the I/O bitmap for \p vm
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*
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@ -407,11 +407,11 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
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case MSR_IA32_MTRR_FIX4K_F0000:
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case MSR_IA32_MTRR_FIX4K_F8000:
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{
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#ifdef CONFIG_MTRR_ENABLED
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v = read_vmtrr(vcpu, msr);
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#else
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err = -EACCES;
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#endif
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if (!vm_hide_mtrr(vcpu->vm)) {
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v = read_vmtrr(vcpu, msr);
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} else {
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err = -EACCES;
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}
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break;
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}
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case MSR_IA32_BIOS_SIGN_ID:
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@ -549,11 +549,11 @@ int32_t wrmsr_vmexit_handler(struct acrn_vcpu *vcpu)
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case MSR_IA32_MTRR_FIX4K_F0000:
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case MSR_IA32_MTRR_FIX4K_F8000:
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{
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#ifdef CONFIG_MTRR_ENABLED
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write_vmtrr(vcpu, msr, v);
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#else
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err = -EACCES;
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#endif
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if (!vm_hide_mtrr(vcpu->vm)) {
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write_vmtrr(vcpu, msr, v);
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} else {
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err = -EACCES;
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}
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break;
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}
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case MSR_IA32_BIOS_SIGN_ID:
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@ -12,8 +12,6 @@
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#include <vm.h>
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#include <logmsg.h>
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#ifdef CONFIG_MTRR_ENABLED
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#define MTRR_FIXED_RANGE_ALL_WB (MTRR_MEM_TYPE_WB \
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| (MTRR_MEM_TYPE_WB << 8U) \
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| (MTRR_MEM_TYPE_WB << 16U) \
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@ -266,5 +264,3 @@ uint64_t read_vmtrr(const struct acrn_vcpu *vcpu, uint32_t msr)
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return ret;
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}
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#endif /* CONFIG_MTRR_ENABLED */
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@ -256,9 +256,7 @@ struct acrn_vcpu_arch {
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/* per vcpu lapic */
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struct acrn_vlapic vlapic;
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#ifdef CONFIG_MTRR_ENABLED
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struct acrn_vmtrr vmtrr;
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#endif
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int32_t cur_context;
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struct cpu_context contexts[NR_WORLD];
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@ -221,6 +221,7 @@ void vrtc_init(struct acrn_vm *vm);
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#endif
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bool is_lapic_pt(const struct acrn_vm *vm);
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bool vm_hide_mtrr(const struct acrn_vm *vm);
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#endif /* !ASSEMBLER */
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@ -50,7 +50,8 @@
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#define SECURE_WORLD_ENABLED (1UL << 0U) /* Whether secure world is enabled */
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#define LAPIC_PASSTHROUGH (1UL << 1U) /* Whether LAPIC is passed through */
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#define IO_COMPLETION_POLLING (1UL << 2U) /* Whether need hypervisor poll IO completion */
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#define CLOS_REQUIRED (1UL << 3U) /* Whether CLOS is required */
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#define CLOS_REQUIRED (1UL << 3U) /* Whether CLOS is required */
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#define HIDE_MTRR (1UL << 4U) /* Whether hide MTRR from VM */
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/**
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* @brief Hypercall
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