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hv: more cleanup for pci.h 

Don't have any logical changes.
- add more common PCI macros
- remove redundant definitions in dmar_parse.c
- move all the common mascos from vpci.h to pci.h

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Zide Chen 2018-10-23 10:05:06 -07:00 committed by lijinxia
parent e24899d9c9
commit bc4f82d1d1
4 changed files with 105 additions and 39 deletions
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2
hypervisor/Makefile
View File

@ -99,9 +99,7 @@ INCLUDE_PATH += include/arch/x86
INCLUDE_PATH += include/arch/x86/guest
INCLUDE_PATH += include/debug
INCLUDE_PATH += include/public
ifeq ($(CONFIG_PARTITION_MODE),y)
INCLUDE_PATH += include/dm
endif
INCLUDE_PATH += bsp/include
INCLUDE_PATH += bsp/include/$(CONFIG_PLATFORM)
INCLUDE_PATH += boot/include

9
hypervisor/boot/dmar_parse.c
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@ -6,13 +6,10 @@
#ifdef CONFIG_DMAR_PARSE_ENABLED
#include <hypervisor.h>
#include "pci.h"
#include "vtd.h"
#include "acpi.h"
#define PCI_CONFIG_ADDRESS 0xcf8
#define PCI_CONFIG_DATA 0xcfc
#define PCI_CONFIG_ACCESS_EN 0x80000000
enum acpi_dmar_type {
ACPI_DMAR_TYPE_HARDWARE_UNIT = 0,
ACPI_DMAR_TYPE_RESERVED_MEMORY = 1,
@ -148,8 +145,8 @@ static uint8_t get_secondary_bus(uint8_t bus, uint8_t dev, uint8_t func)
{
uint32_t data;
pio_write32(PCI_CONFIG_ACCESS_EN | (bus << 16) | (dev << 11) |
(func << 8) | 0x18, PCI_CONFIG_ADDRESS);
pio_write32(PCI_CFG_ENABLE | (bus << 16) | (dev << 11) |
(func << 8) | 0x18, PCI_CONFIG_ADDR);
data = pio_read32(PCI_CONFIG_DATA);

114
hypervisor/include/dm/pci.h
View File

@ -30,30 +30,118 @@
#ifndef PCI_H_
#define PCI_H_
#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
/*
* PCIM_xxx: mask to locate subfield in register
* PCIR_xxx: config register offset
* PCIC_xxx: device class
* PCIS_xxx: device subclass
* PCIP_xxx: device programming interface
* PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
* PCID_xxx: device ID
* PCIY_xxx: capability identification number
* PCIZ_xxx: extended capability identification number
*/
/* some PCI bus constants */
#define PCI_BUSMAX 0xFFU
#define PCI_SLOTMAX 0x1FU
#define PCI_FUNCMAX 0x7U
#define PCI_BAR_COUNT 0x6U
#define PCI_REGMAX 0xFFU
#define PCIR_VENDOR 0x00U
#define PCIR_DEVICE 0x02U
#define PCIR_COMMAND 0x04U
#define PCIR_REVID 0x08U
#define PCIR_SUBCLASS 0x0AU
#define PCIR_CLASS 0x0BU
#define PCIR_HDRTYPE 0x0EU
#define PCIM_HDRTYPE_NORMAL 0x00U
#define PCIM_MFDEV 0x80U
#define PCIC_BRIDGE 0x06U
#define PCIS_BRIDGE_HOST 0x00U
#define PCI_BUS(bdf) (((bdf) >> 8U) & 0xFFU)
#define PCI_SLOT(bdf) (((bdf) >> 3U) & 0x1FU)
#define PCI_FUNC(bdf) ((bdf) & 0x7U)
/* I/O ports */
#define PCI_CONFIG_ADDR 0xCF8U
#define PCI_CONFIG_DATA 0xCFCU
#define PCI_CFG_ENABLE 0x80000000U
/* PCI config header registers for all devices */
#define PCIR_VENDOR 0x00U
#define PCIR_DEVICE 0x02U
#define PCIR_COMMAND 0x04U
#define PCIM_CMD_INTxDIS 0x400U
#define PCIR_STATUS 0x06U
#define PCIM_STATUS_CAPPRESENT 0x0010U
#define PCIR_REVID 0x08U
#define PCIR_SUBCLASS 0x0AU
#define PCIR_CLASS 0x0BU
#define PCIR_HDRTYPE 0x0EU
#define PCIM_HDRTYPE 0x7FU
#define PCIM_HDRTYPE_NORMAL 0x00U
#define PCIM_HDRTYPE_BRIDGE 0x01U
#define PCIM_MFDEV 0x80U
#define PCIR_BARS 0x10U
#define PCIM_BAR_SPACE 0x01U
#define PCIM_BAR_IO_SPACE 0x01U
#define PCIM_BAR_MEM_TYPE 0x06U
#define PCIM_BAR_MEM_32 0x00U
#define PCIM_BAR_MEM_1MB 0x02U
#define PCIM_BAR_MEM_64 0x04U
#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
#define PCIR_CAP_PTR 0x34U
/* config registers for header type 1 (PCI-to-PCI bridge) devices */
#define PCIR_PRIBUS_1 0x18U
#define PCIR_SECBUS_1 0x19U
#define PCIR_SUBBUS_1 0x1AU
/* Capability Register Offsets */
#define PCICAP_ID 0x0U
#define PCICAP_NEXTPTR 0x1U
/* Capability Identification Numbers */
#define PCIY_MSI 0x05U
#define PCIY_MSIX 0x11U
/* PCI Message Signalled Interrupts (MSI) */
#define PCIR_MSI_CTRL 0x02U
#define PCIM_MSICTRL_64BIT 0x80U
#define PCIM_MSICTRL_MSI_ENABLE 0x01U
#define PCIR_MSI_ADDR 0x4U
#define PCIR_MSI_ADDR_HIGH 0x8U
#define PCIR_MSI_DATA 0x8U
#define PCIR_MSI_DATA_64BIT 0xCU
#define PCIR_MSI_MASK 0x10U
#define PCIM_MSICTRL_MMC_MASK 0x000EU
#define PCIM_MSICTRL_MME_MASK 0x0070U
/* PCI device class */
#define PCIC_BRIDGE 0x06U
#define PCIS_BRIDGE_HOST 0x00U
/* MSI-X definitions */
#define PCIR_MSIX_CTRL 0x2U
#define PCIR_MSIX_TABLE 0x4U
#define PCIR_MSIX_PBA 0x8U
#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000U
#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000U
#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FFU
#define PCIM_MSIX_BIR_MASK 0x7U
#define PCIM_MSIX_VCTRL_MASK 0x1U
#define MSIX_CAPLEN 12U
#define MSIX_TABLE_ENTRY_SIZE 16U
union pci_bdf {
uint16_t value;
struct {
uint8_t f : 3; /* BITs 0-2 */
uint8_t d : 5; /* BITs 3-7 */
uint8_t b; /* BITs 8-15 */
} bits;
};
enum pci_bar_type {
PCIBAR_NONE = 0,
PCIBAR_MEM32,
PCIBAR_MEM64,
};
static inline uint32_t pci_bar_offset(uint32_t idx)
{
return 0x10U + (idx << 2U);

19
hypervisor/include/dm/vpci.h
View File

@ -30,8 +30,7 @@
#ifndef VPCI_H_
#define VPCI_H_
#define PCI_BAR_COUNT 0x6U
#define PCI_REGMAX 0xFFU
#include <pci.h>
struct pci_vdev;
struct pci_vdev_ops {
@ -46,22 +45,6 @@ struct pci_vdev_ops {
uint32_t bytes, uint32_t *val);
};
union pci_bdf {
uint16_t value;
struct {
uint8_t f : 3; /* BITs 0-2 */
uint8_t d : 5; /* BITs 3-7 */
uint8_t b; /* BITs 8-15 */
} bits;
};
enum pci_bar_type {
PCIBAR_NONE = 0,
PCIBAR_MEM32,
PCIBAR_MEM64,
};
struct pci_bar {
uint64_t base;
uint64_t size;