hv: cpuid: add several leaf to per-cpu list in hybrid architecture
P-cores and E-cores accessing leaf 0x2U/0x14U/0x16U/0x18U/0x1A/0x1C/0x80000006U will have different information in hybrid architecture. So add them to per-cpu list in hybrid architecture and directly return the physical value. Note: 0x14U is hided and return 0. Tracked-On: #8608 Signed-off-by: Haiwei Li <haiwei.li@intel.com>
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@ -594,8 +594,11 @@ static inline void percpu_cpuid_init(void)
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/* hybrid related percpu leaves*/
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if (pcpu_has_cap(X86_FEATURE_HYBRID)) {
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/* 0x4U, 0x6U */
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uint32_t hybrid_leaves[] = {CPUID_CACHE, CPUID_THERMAL_POWER};
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/* 0x2U, 0x4U, 0x6U, 0x14U, 0x16U, 0x18U, 0x1A, 0x1C, 0x80000006U */
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uint32_t hybrid_leaves[] = {CPUID_TLB, CPUID_CACHE,
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CPUID_THERMAL_POWER, CPUID_FREQ, CPUID_ADDR_TRANS,
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CPUID_MODEL_ID, CPUID_LAST_BRANCH_RECORD,
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CPUID_EXTEND_CACHE};
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memcpy_s((pcpu_cpuids.leaves + pcpu_cpuids.leaf_nr * sizeof(uint32_t)),
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sizeof(hybrid_leaves), hybrid_leaves, sizeof(hybrid_leaves));
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pcpu_cpuids.leaf_nr += sizeof(hybrid_leaves)/sizeof(uint32_t);
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@ -639,7 +642,8 @@ int32_t set_vcpuid_entries(struct acrn_vm *vm)
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case CPUID_THERMAL_POWER:
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result = set_vcpuid_thermal_power(vm);
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break;
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case 0x07U:
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/* 0x07U */
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case CPUID_EXTEND_FEATURE:
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init_vcpuid_entry(i, 0U, CPUID_CHECK_SUBLEAF, &entry);
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if (entry.eax != 0U) {
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pr_warn("vcpuid: only support subleaf 0 for cpu leaf 07h");
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@ -658,23 +662,25 @@ int32_t set_vcpuid_entries(struct acrn_vm *vm)
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#endif
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result = set_vcpuid_entry(vm, &entry);
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break;
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case 0x12U:
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/* 0x12U */
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case CPUID_SGX_CAP:
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result = set_vcpuid_sgx(vm);
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break;
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/* These features are disabled */
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/* PMU is not supported except for core partition VM, like RTVM */
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case 0x0aU:
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/* 0x0aU */
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case CPUID_ARCH_PERF_MON:
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if (is_pmu_pt_configured(vm)) {
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init_vcpuid_entry(i, 0U, 0U, &entry);
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result = set_vcpuid_entry(vm, &entry);
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}
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break;
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/* Intel RDT */
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case 0x0fU:
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/* 0xFU, Intel RDT */
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case CPUID_RDT_MONITOR:
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break;
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/* Intel RDT */
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case 0x10U:
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/* 0x10U, Intel RDT */
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case CPUID_RDT_ALLOCATION:
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#ifdef CONFIG_VCAT_ENABLED
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if (is_vcat_configured(vm)) {
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result = set_vcpuid_vcat_10h(vm);
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@ -682,12 +688,10 @@ int32_t set_vcpuid_entries(struct acrn_vm *vm)
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#endif
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break;
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/* Intel Processor Trace */
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case 0x14U:
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/* PCONFIG */
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case 0x1bU:
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/* V2 Extended Topology Enumeration Leaf */
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case 0x1fU:
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/* 0x14U, Intel Processor Trace */
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case CPUID_TRACE:
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/* 0x1BU, PCONFIG */
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case CPUID_PCONFIG:
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break;
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default:
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init_vcpuid_entry(i, 0U, 0U, &entry);
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@ -933,7 +937,8 @@ void guest_cpuid(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t
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} else {
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/* percpu related */
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switch (leaf) {
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case 0x01U:
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/* 0x01U */
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case CPUID_FEATURES:
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guest_cpuid_01h(vcpu, eax, ebx, ecx, edx);
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break;
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@ -947,23 +952,35 @@ void guest_cpuid(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t
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guest_cpuid_06h(vcpu->vm, eax, ebx, ecx, edx);
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break;
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case 0x0bU:
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/* 0x0BU */
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case CPUID_EXTEND_TOPOLOGY:
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guest_cpuid_0bh(vcpu, eax, ebx, ecx, edx);
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break;
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case 0x0dU:
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/* 0x0dU */
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case CPUID_XSAVE_FEATURES:
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guest_cpuid_0dh(vcpu, eax, ebx, ecx, edx);
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break;
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case 0x19U:
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/* 0x14U for hybrid arch */
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case CPUID_TRACE:
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*eax = 0U;
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*ebx = 0U;
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*ecx = 0U;
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*edx = 0U;
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break;
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/* 0x19U */
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case CPUID_KEY_LOCKER:
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guest_cpuid_19h(vcpu, eax, ebx, ecx, edx);
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break;
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case 0x1fU:
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/* 0x1fU */
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case CPUID_V2_EXTEND_TOPOLOGY:
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guest_cpuid_1fh(vcpu, eax, ebx, ecx, edx);
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break;
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case 0x80000001U:
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/* 0x80000001U */
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case CPUID_EXTEND_FUNCTION_1:
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guest_cpuid_80000001h(vcpu, eax, ebx, ecx, edx);
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break;
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@ -171,16 +171,26 @@
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#define CPUID_CACHE 4U
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#define CPUID_THERMAL_POWER 6U
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#define CPUID_EXTEND_FEATURE 7U
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#define CPUID_ARCH_PERF_MON 0xAU
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#define CPUID_EXTEND_TOPOLOGY 0xBU
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#define CPUID_XSAVE_FEATURES 0xDU
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#define CPUID_RDT_MONITOR 0xFU
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#define CPUID_RDT_ALLOCATION 0x10U
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#define CPUID_SGX_CAP 0x12U
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#define CPUID_TRACE 0x14U
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#define CPUID_FREQ 0x16U
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#define CPUID_ADDR_TRANS 0x18U
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#define CPUID_KEY_LOCKER 0x19U
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#define CPUID_MODEL_ID 0x1AU
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#define CPUID_PCONFIG 0x1BU
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#define CPUID_LAST_BRANCH_RECORD 0x1CU
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#define CPUID_V2_EXTEND_TOPOLOGY 0x1FU
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#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000U
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#define CPUID_EXTEND_FUNCTION_1 0x80000001U
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#define CPUID_EXTEND_FUNCTION_2 0x80000002U
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#define CPUID_EXTEND_FUNCTION_3 0x80000003U
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#define CPUID_EXTEND_FUNCTION_4 0x80000004U
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#define CPUID_EXTEND_CACHE 0x80000006U
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#define CPUID_EXTEND_INVA_TSC 0x80000007U
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#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008U
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